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RC Extraction with black box option

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Advanced Member level 5
Jan 9, 2012
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I am interested in running the LVS for the top hierarchal level which includes already verified layout blocks. Hence the top abstract contains those cells plus the interconnection between them and to the pads.

It is recommended by Cadence help to run LVS by treating the lower layout cells as a back box.

I couldn't understand the idea of black box because from what I read it looks to me that the tool treat those boxes as a box with the extended pins for next verification of LVS, and then the QRC extractor will only exctract the parasatic of the top level connections.

Of course I am not sure about my conclusion, but if my understanding is right it means the post-layout simulation will only reflect the fact due to the top-level parasitic.

It would be helpful if you explain me the advantage of black box and the difference in case if I used the regular LVS without black box.

Thank you in advance

Best Regards

I wouldn't trust blackboxing for my designs... I have only considered it as a way to - arguably - speed up the process. But as soon as you have some routing on top of things, you would like to see how they affect the blocks underneath. I guess, for some cells, you might have them completely isolated from anything routed on top, like IO cells, for example, then it could make some kind of sense.
The main reason, I think, for blackbox extraction methodology, is to reduce the extraction time and size of a post-layout netlist.
This benefit is achieved if you have a cell that is instantiated multiple times in a hierarchical design (up to dozens or hundreds of times).
The idea is that you extract a cell once, then instantiate it multiple time.

The cell is extracted at its level, once.
Then, you do top-level extraction, with black boxing (or grayboxing) of extracted cells.
Then, in SPICE deck, or in hierarchy editor, you instantiate the top level block, and lower-level cells.

The drawback of this approach is that many parasitic effects get missed, or get messed up.
For example:

- coupling form upper level routing to inside the cell - will be decoupled (i.e. grounded), so that if there is a critical aggressor to victim coupling - it will be completely missed.

- capacitive interaction between the blackboxes cells.

- resistive effects - if long-range routing goes through the cell hierarchy level.

- many others.
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