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RC extraction from a tool like Synopsys Star-RC will spit out an HSPICE SUBCKT netlist with Resistances and capacitances corresponding to the different layers in your layout in addition to the transistors. It might include the area/perimeter of your transistors but the best estimate of your net area should come from looking at layout directly. RC extraction is useful for characterization of your cells since it includes parasitic resistances/capacitances due to contacts and wires. StarRC has the capability to show coupling capacitance report, lump all capacitance to ground, do R only or C only capacitance etc. The general output format of the extracted netlist is something like this:
I mainly deal with transistor models, HSPICE simulations and extraction. Hence, I am not very familiar with flows beyond extraction and someone else might be able to provide you with detailed information regarding SDF/SPEF. As far as I understand, SPF file is what you get after RC extraction. You can use it in tools like PrimeTime to get SDF, which has the cell delay information. This is calculated using the information in the SPF file (I think).
The R and C's are not necessarily parasistic in extraction, they would include interconnect RC as well. The parasitic components are from the FEOL (Front-End-of-Line) and MOL(Middle-of-Line) layers like local interconnects, contact R and fringing C.