random generator verilog source code

[openwindows]

verilog random number generator

who can post?

 

[gauiver]

random number generator verilog

there is a confusion here. are u asking about the internal structure of saics thnat what internal structure comes out or something more related to some software like max+2. plz clear this but in any case u will find this useful



1 warning (-5 posts, - 20 points) , attachment deleted
1 - This post has nothing in common with the request made
2- This file was uploaded 1000 times on elektroda. And most of all
it is freely availlable on the web !

 

[gauiver]

verilog random

vow thats more than a whole course in a semester. well u can find alot on this site there are a lot of e-books on asic on asychronous designing and also do check this attachment it will also be helpful. i think that u should rfeally check this site becaz i think i have seen quite a big amount of data on asychronous design, about 20mb. and by the way what are u doing becaz i haven't studied all of them in my course.

 

[dainis]

random in verilog

Look Verilog and VHDL CRC code generator:
https://www.easics.be/webtools/crctool

 

[philewar]

$random verilog

who can post?

Hello Benny,

Do you mean random number generator?

 

[it_boy]

random verilog

Hi Benny,
If it is just a random number generator you want, attached is a pseudo random number with 15-bit polynomial generating a 64 bit parallel output

 

[dainis]

verilog random number

http://www.deeps.org/hdl_models/index.html
http://www.deeps.org/hdl_models/lfsr_counter.html
http://www.deeps.org/hdl_models/rand.html

 

[philewar]

verilog random function

Hello,

How about true random number generator?

I think it must read some real random seed external, right?

Thx.

 

[it_boy]

$random in verilog

I think nothing like a true random number. the randomness depends on the length of the seed value and the polynomial used.
Whatever be the seed value used, the random pattern a random pattern generator can generate will be same, depending on the polynomial. Seed value only defines the starting value of the random number.
Somebody please correct me if I am wrong

 

[philewar]

random number generator in verilog

Hello it_boy,

hmm, maybe you are right.
What about if the source is from a white noise or sth. like?

 

[maxplus1000]

verilog $random

Could this random generator be synthesisable?

 

[philewar]

verilog random generator

LFSR is synthesisable while other pseudo random number generators are only for simulation.

 

[maniasonic]

verilog random number generation

a true random generator is definitively impossible to come out as a synthesible digital design...sigh...

 

[samlee]

random number generator verilog code

How random it is? I mean how many number will the value be repeat again?

 

[always@smart]

prbs verilog

Dear all,
Anyone has the code or info for the Random number generator and the Random number verifier. I've to design for the transceiver, which transmiter has 8-bit PRBS and the receiver has PRBS verification.

Any infomation is highly appreciated.

Thank you in advance.

Regards,
Alwys@smart

 

[baonguyenpro]

pseudo random number generator verilog

Linear Feedback Shift Register
Pseudo Random Binary Sequence
You can find in book: "Rapid Prototyping of Digital System"
"HDL Chip Design"
Application Note of Altera, Xilinx.

 

[sparso]

prbs generator verilog

I need to design a prbs generator and analyzer for a loop-back test. Any idea where I can get some info?

 

[jasonkee111]

I have use a simple LFSR to generare random number. Set of random number are pass through to FFT(power in db vs freq). However, the freq response is increasing at low freq. Then only maintain roughly flat for higher freq. Is there any problem with increasing at low freq?

If yes may i know the reason?

FYI, lot of white noise freq response is almost flat from low to high freq.

Thanks