ramp voltage generation using SPI DAC in VHDL

[jimmykk]

hI
i WANT to obtain an analog ramp voltage from 0 to 3 V by using a FPGA Board and a DAC(offboard). the period of ramp voltage should be 100ms and this should be done by a 14 BIT DAC operating with 5Mhz clock . aNY SUGGESTIONS or VHDL code available would be very helpful for me
thanks

 

[barry]

Assuming your full scale voltage is 3V. Your DAC code needs to ramp from 0 to 16383 in 100mS. That means each step occurs in 6.103 microseconds. This does not have a nice integer relation to 5MHz. There are several approaches you can take, such as:

1) Use a PLL (if your FPGA has one)to generate an appropriate sampling frequency. This might not be acceptable due the jitter associated with the PLL.
2) Change your ramp requirement. If you increment your DAC every 31 5MHz clocks, you'll get a ramp time of 101.6mS.
3) Adjust your resolution. If you can accept 13 bits resolution(8192), then you can increment your DAC code by 2 every 61 5MHz clocks. This would give a ramp of 61/5MHz*8192= .9994mS.

 

[FvM]

A NCO can generate the ramp with almost exact frequency. https://en.wikipedia.org/wiki/Numerically_controlled_oscillator

 

[barry]

A NCO can generate the ramp with almost exact frequency. https://en.wikipedia.org/wiki/Numerically_controlled_oscillator

This could provide the exact period, but the ramp would have some non-linearities (uneven spacing between steps). It might be perfectly suitable, though.

 

[FvM]

The "uneven spacing" is a consequence of working with a clock frequency that's no integer multiple of the nominal step frequency. Considering real DAC properties, e.g. DNL, the difference is neglibible.

 

[jimmykk]

2) Change your ramp requirement. If you increment your DAC every 31 5MHz clocks, you'll get a ramp time of 101.6mS.
3) Adjust your resolution. If you can accept 13 bits resolution(8192), then you can increment your DAC code by 2 every 61 5MHz clocks. This would give a ramp of 61/5MHz*8192= .9994mS.

Thanks for your response.....I can go with any of these two options but i did not get the idea of how to implement this logic in a vhdl code.Sorry for my dumb question by 31 5MHz clocks and 61 5 MHz clocks....you mean that incrementing code at every 31 and 61 falling edge of 5 MHz clock.

 

[barry]

Yes. If you have a counter that generates a pulse every 31 clocks, the period of those pulses would be 31/5MHz=6.2uS. If you use those pulses (one clock period wide) to enable your DAC counter, the DAC counter will count from 0 to 16383 in 101.5808 milliseconds.

 

[jimmykk]

Thanks....i think that would definitely work....but what i have thought is to get only output in the range of 0 to 2.9V in 100ms(though full scale voltage is 3.3V). This would give me RAMP CODE from 0 to 14398. then i would generate a pulse every 34 clocks so that period becomes 6.8 us and can manage with 14705 values. i can generate that pulse but question is implementing the counter here.

 

[barry]

What is your question about implementing a counter? That's a fundamental construct.

 

[jimmykk]

The problem is that i have to implement counter which will increment 14398/5000 and 14398/20000 with every iteration for increasing the amplitudes of incoming signals between 50khz(5000periods) and 200khz(20000periods) respectively for 100ms(for voltage between 0to2.9V).

 

[FvM]

I don't get exactly the meaning of this caculation, but a versatile method to implement ramps with arbitrary fractional increment has been suggested in post #3. I'm sure it can work for this problem too.