module RAM (
address,
we,
clock,
data,
q);
input [7:0] address;
input we;
input clock;
input [7:0] data;
output [7:0] q;
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
lpm_ram_dq lpm_ram_dq_component (
.address (address),
.inclock (clock),
.data (data),
.we (we),
.q (sub_wire0));
defparam
lpm_ram_dq_component.intended_device_family = "FLEX10K",
lpm_ram_dq_component.lpm_width = 8,
lpm_ram_dq_component.lpm_widthad = 8,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.use_eab = "ON",
lpm_ram_dq_component.lpm_hint = "MAXIMUM_DEPTH=256",
lpm_ram_dq_component.lpm_type = "LPM_RAM_DQ",
lpm_ram_dq_component.lpm_file = "nabilcpu.mif";
endmodule