RAM Modeling in Verilog [50 to 100 points on solution]

[tariq786]

ram verilog modeling

Hi friends,
I have modeled RAM in verilog. The code is simple see below. I can read and write it without any problem. When i try to access it from the test bench using a new instance, i get xxxxxxxxxxxxxxxxx. Can anyone guide me towards the solution.
Note that i have to access RAM in different module of a larger project and i have to create RAM instances to access RAM.

The one who helps get 50 to 100 points.


timescale 1ns / 1ps

module REGFILE(
output reg [127] Rdata,
input [127] Wdata,
input clk,
input Read,
input Write
);


reg [127] RAM;

always @(posedge clk,Read,Write)
if(Read)
begin
Rdata = RAM;
end
else if (Write)
begin
RAM = Wdata;
end


endmodule







/***********************************************Test Bench ********/
`timescale 1ns / 10ps


module test;


reg clk;
reg Read, Write;
reg Read1, Write2;
reg [127] X;

wire [127] Y;
wire [127] Z;


initial
begin

clk = 0;
X = 128'b0;

end



always
begin
#5 clk = ~clk;
end



initial
#15 Write = 1;
initial
#25 Write = 0; //stop writing

initial
begin #25 Read = 1; Read1 = 1; end

initial
begin #35 Read = 0; Read1 = 0; end


REGFILE u0(.Rdata(Y),
.Wdata(X),
.clk(clk),
.Read(Read),
.Write(Write)
);

REGFILE u1(.Rdata(Z),
.Wdata(X),
.clk(clk),
.Read(Read1),
.Write(Write1)
);


initial
$monitor($time,",X is %h, Y is %h, Z is %h Read is %d, Write is %d \n",X,Y,Z,Read,Write);

endmodule






/**************** Simulation Result **********************************/


# 0,X is 00000000000000000000000000000000, Y is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, Z is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Read is x, Write is x
#
# 15,X is 00000000000000000000000000000000, Y is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx, Z is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Read is x, Write is 1
#
# 25,X is 00000000000000000000000000000000, Y is 00000000000000000000000000000000, Z is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Read is 1, Write is 0
#
# 35,X is 00000000000000000000000000000000, Y is 00000000000000000000000000000000, Z is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Read is 0, Write is 0

Added after 1 hours 10 minutes:

To make things more clearer, how would i read and write RAM in different modules of my project making sure that i have one single RAM whom i am reading or writing in different modules of my project?

 

[karper1986]

sram read write verilog code and test bench

Hi tariq786,

I`m new in verilog, dont know if it will work, can try this code in your mem module, if dont please sorry.

timescale 1ns / 1ps

module REGFILE(
output reg [127] Rdata,
input [127] Wdata,
input clk,
input Read,
input Write
);


reg [127] RAM;

always @(posedge clk)
begin
if(Write == 1) begin

RAM <= Wdata;end
end

assign Rdata = RAM;

endmodule

Best regards,
Karper

 

[mkanimozhivlsi]

ram, verilog

Hi tariq786,

Here is the corrected code for your RAM Module design.


Regards
Kanimozhi.M

 

[kalyansumankv]

%h write verilog

Hi Friends,

I found the following from your Question.,

1. The size of the memory is not defined.
-- to the best of my knowledge the above code just writes one value into ROM,when Write is high and read back when Read is high

2. there is no where the memory declaration is given.
like reg [07:00] mem [15:00]

3. before u run the test bench please load the initial values in the memory,
for this you will have a feature in simulator to load the values into the memory.
(the suggestion given by mkanimozhivlsi works, when there is only one element in the memory,)