RAM implementation on NEXSYS2 Digilent board

[sai1711]

Hi All,
I have been playing around with NEXSYS2 Board for sometime now.
I have written a code on VHDL for RAM and Random number generator.
My problem is, I cant find a way to implement RAM on the Nexsys 2 Board.
Any help in directing me towards the Pin Numbers pertaining to RAm would be extremely helpful.
Also needed pointers on connecting the output to a DAC.
Sincerely
Sai
PS: Nothing was clear on the User manual of Nexsys2.

 

[TrickyDicky]

When you say you have written ram - do you mean you have written an SRAM controller or written code thay should infer or instantiate and internal ram block?

 

[sai1711]

I want to implement the following code. on Nexsys 2 board

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY ram_simple IS
PORT (
SIGNAL data : IN std_logic_vector(7 DOWNTO 0);
SIGNAL address : IN std_logic_vector(4 DOWNTO 0);
SIGNAL we, inclock, outclock : IN std_logic;
SIGNAL q : OUT std_logic_vector(7 DOWNTO 0));


END ram_simple;

ARCHITECTURE fe2 OF ram_simple IS

TYPE mem_type IS ARRAY ( 31 DOWNTO 0) OF std_logic_vector (7 DOWNTO 0);
SIGNAL mem : mem_type;
SIGNAL address_int : unsigned(4 DOWNTO 0);

BEGIN -- ex2
l0 : PROCESS (inclock,outclock, we, address)

BEGIN -- PROCESS
IF (inclock = '1' AND inclock'event) THEN
address_int <= unsigned(address);
IF we = '1' THEN
mem(To_integer(unsigned(address))) <= data;
END IF;
END IF;
IF (outclock = '1' AND outclock'event) THEN
q <= mem(to_integer(address_int));
END IF;

END PROCESS;

END fe2;

 

[phobos1]

Hi try templates from the xilinx ise software it will have all types of ram implementations its a bulb icon in the top right.

 

[sai1711]

hi phobos, I think, I found the general UCF file from Digilent, I will try on that and report the problems if I encounter. Thanks again
Sai

- - - Updated - - -

Not working;
I need to check something else.

 

[TrickyDicky]

first of all, the inclock and outclock should be in separate processes.
secondly, you are registering the read address at the inclock and then reading in the outclock. The address should be registered in the outclock process.

The UCF file wont help you here as you're not following the templates properly.

 

[sai1711]

first of all, the inclock and outclock should be in separate processes.
secondly, you are registering the read address at the inclock and then reading in the outclock. The address should be registered in the outclock process.

The UCF file wont help you here as you're not following the templates properly.

Ahh yeah I faced that problem, you are right, now I know, Inclock and outclock should be in a separate process, you are right. I used another code, and did with the UCF files, its working now.
I used single clock in the new code. Thanks again.