Quick Verilog question

[vlad928]

I have a wire that I want to assign to my output. I have tried using x1 = out1 and it gives an error. Here is a pseudo code of what I am talking about.

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
module test (out1, in1);
output out1;
input in1;
wire x1;
 
not (x1, in1);
 
wire x1 = out1;
 
endmodule

---

 

[hamid159]

the 8th line is incorrect.. you must replace "wire" with "assign".

 

[ads-ee]

It should also have the x1 and out1 swapped.

assign out1 = x1;