nassim_el85
Member level 4
Hi
In “A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration
Grace, C.R.; Hurst, P.J.; Lewis, S.H.; Solid-State Circuits, IEEE Journal of “
In first paragraph of the second page says: “Applying a queue with one
SHA to a pipelined ADC requires that fc (conversion frequency) is at least one and
a half times larger than fs (input sampling frequency) [5]. “
I want to know why?
The referred paper is: “[5] E. B. Blecker, T. M. McDonald, O. E. Erdo˘gan, P. J. Hurst, and S. H. Lewis, “Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1059–1062, Jun. 2003.”
I can’t find the answer in this reference. Can any one explain me the reason or referred me to another?
In “A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration
Grace, C.R.; Hurst, P.J.; Lewis, S.H.; Solid-State Circuits, IEEE Journal of “
In first paragraph of the second page says: “Applying a queue with one
SHA to a pipelined ADC requires that fc (conversion frequency) is at least one and
a half times larger than fs (input sampling frequency) [5]. “
I want to know why?
The referred paper is: “[5] E. B. Blecker, T. M. McDonald, O. E. Erdo˘gan, P. J. Hurst, and S. H. Lewis, “Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue,” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1059–1062, Jun. 2003.”
I can’t find the answer in this reference. Can any one explain me the reason or referred me to another?