Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

questions regarding the drop-out voltage of a DC regulator

Status
Not open for further replies.

rickmhusa

Newbie level 3
Joined
Jul 26, 2009
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
San Jose
Activity points
1,307
dropout questione

Hi,

Frequently, we see papers state the drop-out voltage of a regulator is 200mV when Iout(max) = 100mA. If I understand it correctly, it means the Vds(sat) of the power MOS (let's assume a PMOS power MOS is used) is 200mV. Also |Vgs| - |Vth| = Vov of the power MOS is nearly equal to 200mV when Iout = 100mA. Am I correct? If so, when Iout = 0, the Vov of the power MOS will be very small. In fact, it may will be in a sub-threshold region, since the device size is large and Iout is small. If the power MOS is in the sub-threshold region, how will the regulator regulate the output as Iout = 0?

I am interested in the design of a low drop-out regulator, and I am just a beginner. Perhaps someone who is expert on this topic can help me out. Thanks alots.
 

rickmhusa

Newbie level 3
Joined
Jul 26, 2009
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
San Jose
Activity points
1,307
questionnaire about drop outs

Hi smd_lover,

Thank you so much for your reply. I would like to confirm that I understand your reply correctly. If the power MOS goes into the linear region (for a MOS) or into the sub-threshold region (cut-off region) when Iout = 0, it still will be OK with a big enough output capacitance. Am I correct?
 

smd_lover

Member level 1
Joined
Jul 19, 2009
Messages
37
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,288
Location
Netherlands
Activity points
1,455
Re: questions regarding the drop-out voltage of a DC regulat

Yes, suppose the output voltage is too low, there will be current flowing through the mosfet into the output capacitor.
Voltage will rise up until setpoint, then the feedback loop will lower the g-s voltage of the mosfet to zero. No current will flow and the capacitor voltage will stay at that value.
 

rickmhusa

Newbie level 3
Joined
Jul 26, 2009
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
San Jose
Activity points
1,307
Re: questions regarding the drop-out voltage of a DC regulat

Hi smd_lover,

Once again, thank you so much for your reply and patient. I think I got your point this time. Bascially, when Iout increases form 0A to 100mA, the Vgs of the PMOS power device will increase in order to increase the current flows through the device. However, when Iout decreases from 100mA to 0A, the Vgs of the device decreases in order to turn off the PMOS. Also due to the large output capacitance, the output voltage will stay at that value. Am I correct? Thanks alot.
 

dick_freebird

Advanced Member level 5
Joined
Mar 4, 2008
Messages
6,915
Helped
2,025
Reputation
4,054
Reaction score
1,865
Trophy points
1,393
Location
USA
Activity points
55,373
The swing from linear to saturated operation in MOS is a challenge for loop stabilization, but people handle it (by combination of internal design and external component selection).

Some LDOs add a shunt device to deal with the leakage / light load regulation issues, at some cost to efficiency.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top