# questions regarding the drop-out voltage of a DC regulator

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#### rickmhusa

##### Newbie level 3
dropout questione

Hi,

Frequently, we see papers state the drop-out voltage of a regulator is 200mV when Iout(max) = 100mA. If I understand it correctly, it means the Vds(sat) of the power MOS (let's assume a PMOS power MOS is used) is 200mV. Also |Vgs| - |Vth| = Vov of the power MOS is nearly equal to 200mV when Iout = 100mA. Am I correct? If so, when Iout = 0, the Vov of the power MOS will be very small. In fact, it may will be in a sub-threshold region, since the device size is large and Iout is small. If the power MOS is in the sub-threshold region, how will the regulator regulate the output as Iout = 0?

I am interested in the design of a low drop-out regulator, and I am just a beginner. Perhaps someone who is expert on this topic can help me out. Thanks alots.

#### smd_lover

##### Member level 1
how to increase 100ma regulator current

A mos does not go into saturation like a bipolair transistor.
But even then it is not a big deal. With a big enough capacitor at the output, regulation is acceptable.
A nice example/schematic is this one:
http://electronicdesign.com/Articles/ArticleID/9136/9136.html

#### rickmhusa

##### Newbie level 3

Hi smd_lover,

Thank you so much for your reply. I would like to confirm that I understand your reply correctly. If the power MOS goes into the linear region (for a MOS) or into the sub-threshold region (cut-off region) when Iout = 0, it still will be OK with a big enough output capacitance. Am I correct?

#### smd_lover

##### Member level 1
Re: questions regarding the drop-out voltage of a DC regulat

Yes, suppose the output voltage is too low, there will be current flowing through the mosfet into the output capacitor.
Voltage will rise up until setpoint, then the feedback loop will lower the g-s voltage of the mosfet to zero. No current will flow and the capacitor voltage will stay at that value.

#### rickmhusa

##### Newbie level 3
Re: questions regarding the drop-out voltage of a DC regulat

Hi smd_lover,

Once again, thank you so much for your reply and patient. I think I got your point this time. Bascially, when Iout increases form 0A to 100mA, the Vgs of the PMOS power device will increase in order to increase the current flows through the device. However, when Iout decreases from 100mA to 0A, the Vgs of the device decreases in order to turn off the PMOS. Also due to the large output capacitance, the output voltage will stay at that value. Am I correct? Thanks alot.