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[SOLVED] Questions Regarding ADS EM Simulation

Shawn Jobs

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I would like to ask everyone, why does the simulator repeatedly simulate a frequency point in EM simulation? Is there any way to prevent this repetitive behavior, as it is very time-consuming?
1740912183404.png
 
Look at the first paragraph. The simulator declares all.
Check them all out first.
Thank you for your response. Have you encountered a similar issue before? Could you please advise where I should configure and resolve it?
 
Thank you for your response. Have you encountered a similar issue before? Could you please advise where I should configure and resolve it?
I don't know what you simulate. Anything may be reason, there may be multiple reasons.
-The structure might be/have some drawing errors that make the meshing process too complicated
-Ports might be wrongly configured
-Substrate errors, definition faults ?

Anything might be a reason. If you archive (ADS Archive format) your project file, I can verify for you.
 
why does the simulator repeatedly simulate a frequency point in EM simulation?
It seems that you have some very narrowband (high Q) resonance at that frequency, for whatever reason.

Look at the warning in the first part of your first screenshot, and take this serious. The resonance might be some simulation artefact from dielectric layers that are too thick, and ports that are too long or too wide (!) compared to wavelength. All this can create numerical nonsense, and then you run into such trouble.

For example, if you place a pin on the edge of a wide polygon, this will by default create a port across the entire edge length, which you didn't want, and which is too wide -> invalid results.
 
I don't know what you simulate. Anything may be reason, there may be multiple reasons.
-The structure might be/have some drawing errors that make the meshing process too complicated
-Ports might be wrongly configured
-Substrate errors, definition faults ?

Anything might be a reason. If you archive (ADS Archive format) your project file, I can verify for you.

Thank you for your response. I apologize, but due to proprietary processes, I am unable to share my project. However, from the screenshots below, could you identify any issues that I should avoid?

1741086502622.png

--- Updated ---

It seems that you have some very narrowband (high Q) resonance at that frequency, for whatever reason.

Look at the warning in the first part of your first screenshot, and take this serious. The resonance might be some simulation artefact from dielectric layers that are too thick, and ports that are too long or too wide (!) compared to wavelength. All this can create numerical nonsense, and then you run into such trouble.

For example, if you place a pin on the edge of a wide polygon, this will by default create a port across the entire edge length, which you didn't want, and which is too wide -> invalid results.

Thank you for your reply. I also think it might be an issue with the PINs. The PINs I used are all set to the default DOT (Shape), and each one has been placed on the Port of the process device. Could the situation you described still occur under these circumstances?

1741086866259.png

--- Updated ---

It seems that you have some very narrowband (high Q) resonance at that frequency, for whatever reason.

Look at the warning in the first part of your first screenshot, and take this serious. The resonance might be some simulation artefact from dielectric layers that are too thick, and ports that are too long or too wide (!) compared to wavelength. All this can create numerical nonsense, and then you run into such trouble.

For example, if you place a pin on the edge of a wide polygon, this will by default create a port across the entire edge length, which you didn't want, and which is too wide -> invalid results.

Thank you for your reply. I also think it might be an issue with the PINs. The PINs I used are all set to the default DOT (Shape), and each one has been placed on the Port of the process device. Could the situation you described still occur under these circumstances?

1741086866259.png
 
I would not use TML calibration for RFIC EM analysis, the ground is too far away. From my experience, it is better to choose Direct.
--- Updated ---


Your layout for EM looks like a collection of many unrelated layout pieces, why is that?
Momentum will try to calculate the (almost zero) couplings between all 47 ports, and adaptive sweep might hunt for some fake resonances there.
 
Last edited:
I would not use TML calibration for RFIC EM analysis, the ground is too far away. From my experience, it is better to choose Direct.
--- Updated ---


Your layout for EM looks like a collection of many unrelated layout pieces, why is that?
Momentum will try to calculate the (almost zero) couplings between all 47 ports, and adaptive sweep might hunt for some fake resonances there.

The spaces left between the ports are intended for placing FETs, inductors, and capacitors. Since the EM simulation in the Layout cannot directly simulate the FET, I removed it and added ports. Additionally, because I was concerned that the Layout might not perform ideally, I also removed the inductors and capacitors and added ports to facilitate later debugging. This is why there are so many pieces in the final design. (I am not very familiar with RFIC design, so I would like to ask if this design approach is correct and if there are more reasonable design strategies.) Thank you very much for your answer.
 
That sounds ok to me.

So you should now focus on the warning at the very top of your simulation log, and get that solved. You can look at S-parameter results and check which path is causing that resonance where adaptive sweep is hunting for more points.
 
That sounds ok to me.

So you should now focus on the warning at the very top of your simulation log, and get that solved. You can look at S-parameter results and check which path is causing that resonance where adaptive sweep is hunting for more points.

Alright, I will proceed to address the issues highlighted in the simulation log.
 

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