Questions on Xilinx Virtex-4 power up requirements

[gongdori]

Hi all,

In the Xilinx V4 datasheet, there is power supply ramp time requirement (Table 6 in DS595 DC and switching characteristics).
It says that the three voltage rails should be ramp up within 0.2ms to 50 ms. (I assume 0V to the 100%?)
I wonder where this requirement comes from.
Is it needed for the silicon to power up correctly, or is it related to FPGA configuration at power up?
If it is related to FPGA configuration at power up, can it be removed, if the configuration is delayed after powering up?
Thanks,

Gongdori

 

[ea.arun]

my understanding is this ramp up current requirement is not for the configuration...its for the initialization FPGA which you have to make sure to avoid any erroneous behaviour.....
you can relate it to surge current in a capacitor......its something like charging up the internal mosfets(or the equivalent capacitance seen by the power supply) instantaneously at once to stabilize and proceed with configuration or any other function.......

i found an applicatiion note for your reference....please have a look
https://www.ti.com/lit/an/slyt079/slyt079.pdf

 

[gongdori]

Thanks for your help!