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Questions on the top-down analog design flow

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Junior Member level 3
Feb 1, 2008
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basic analog design questions

I was an OK digital designer with very little analog design experience, and I am always very curious to understand a complete analog design flow. From reading some analog textbook and from reading this board regularly, I came up with my own understanding of the top-down analog design flow and hope all of you can help to point out what is missing, what is incorrect or where to get more help. Thank you in advance.

The Top-Down Analog/Mixed-Signal Design Flow (of my understanding)

1. System Level Simulation with System Spec
a. Not clear what the System Spec looks like though.
b. Tool used in this level: Matlab, C, others?

2. Break Down to block level with block level spec
a. Tool used in this level: Matlab, manual, spreadsheet, etc.
b. Again, not clear what the block level spec looks like though?
c. Not clear where to stop going down further before choosing the topology (next step). My understanding is to stop at Opamp (all sorts) level, what are other parallel analog blocks, for example, is bandgap reference considered to be at the same level?

3. Pick and choose the ckt topology for each block and enter into the schematic capture tools.
a. Tools used in this step: schematic entry, for example, composer.
b. Can any ckt topology always be breakable further into more basic building blocks such as current mirror, cascode, differential pair, folded cascode stage, to facilitate the hand calculation in the next step?

4. Hand calculate the ball park transistor sizes (W & L) with the first order equations
a. Is hand calculation always applied to basic building block level (mentioned in 3.b) only?
b. Other than pen and pencil, any tools being used at this level?
c. What if some devices do not belong to any basic building blocks mentioned in 3.b, will this happen and in this case, how to perform hand calculation?

5. Verify with SPICE and iterate
a. Tool used at this step: SPICE of any flavor
b. Normally how far off between hand calculation (step 4) and SPICE simulation?
c. If the simulation results do not meet the spec, do we keep changing the transistor sizes, or do we change the topology?

6. Putting blocks together and run circuit simulation to verify
a. Will SPICE be too slow to handle the job at this level?
b. Since each block is supposed to meet the individual spec before putting together, how many issues to be anticipated when putting together and usually what are the issues?

7. Backend: Layout, Extraction, Post Sim, LVS/DRC
a. Tool used at this level: Virtuoso, Laker, or other flavor of layout editors.

Assuming the above steps correctly represent the analog/mixed-design flow, how much time(%) normally will be spent on the front-end (step 1 to 6) and how much time will be spend on the backend (step 7), and among step 1 to 6, how much time is spent on each?

Thank you for reading.


Member level 2
Mar 14, 2004
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analog design flow


Th algorithm and steps you have mentioned are to some extend correct. Why to some extend?
It really depends on the project You want to work on, your experiences, Do you want to all the project your self or others will make it for you and etc.
As you see, a unique method can not be offered for all the projects in all levels.
It may be interesting to note some thing from Ernestine and use it in this case:
"Things must be broken to simple parts but not simpler."

It is very good to break complex project to smaller parts but some times breaking some thing to very tiny parts make it unusable.

Finally I want to note the important role of experience.

Hope it helped.

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