Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Questions on Sub-1 Volt OTA

Status
Not open for further replies.

promach

Advanced Member level 4
Joined
Feb 22, 2016
Messages
1,199
Helped
2
Reputation
4
Reaction score
5
Trophy points
1,318
Activity points
11,636
Could anyone explain on Obviously, the compensation capacitance CC does not connect Drain to Gate directly around
output transistor M10. It takes a path through cascode device M6, in order to avoid a positive zero.
?

PqojzkV.png
 

Any capacitor shunts a transconductance stage results in a "feedforwad" zero at -Gm/C
M10 here is the transconductance cell but it has a -ve Gm. Hence, you have a right-half plane zero (-[-Gm/C] = Gm/C) which is the worst for stability. One of solutions is to eliminate the feedforward path as done here. I think this book is sansen, essentials of.. , if so, RHP zeros topic is discussed in details in the op amp stability chapter you may revisit it.
 

    promach

    Points: 2
    Helpful Answer Positive Rating
For those interested in Ahuja compensation, Baker's uses "indirect compensation" in his book : **broken link removed** , see page 813, 814 and 815

1624184761397.png



By the way, I am now working on the actual mosfet circuitry implementation, the circuit is not working yet.

Note: I will decrease the Vin+ and Vin- voltage amplitude afterwards.

1624184684760.png


1624184691923.png
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top