Questions and answers on PIC express verification

[nipoon123]

Hi Ladies and Gentleman,
I am 6 months old in Pci express verification , and an eager enthuiastic too,
I would be happy If some one asks me a doubt (query ) on this topic , Ofcourse u are invited to share your knowledge too.Lets share!!

Regards,
Tumcha BAAP

 

[bharat_in]

pci express configuration space

Can you tell me, what is the usage of LOOPBACK state in LTSSM of PCIe?
Thanks in advance for your answer...

 

[tejas_korwarkar]

pcie put into loopback

How big is PCI configuration space in PCI express?
What is the significance of PCI I/O space and PCI memory space?

 

[Guru59]

use of loopback in pcie

Hi NIPPON........

i am new to PCI X-PRESS nomenclature...........

i would like to know the links for the books on PCI-Xpress...........
plz provide free links

 

[GURU_at_net]

pci express loopback master

Hi Nipoon,

I have a doubt regarding the bandwidth calculation of pci e bus.It is expressed in multiples of x . what is the significance of x parameter ?

thanks
G@N

 

[nipoon123]

pci express non posted explanation

Hi G(at)N,
That was a good question.The best part of Pcie -express is that it has a highly scaleable bandwidth.

pay as much you want !!!!

Pci express is a point to point serial topology.So the bandwidth
can be increased by increasing the number of lanes.

The point is that bandwidth is dependent on lanes.

Now the lanes are represented by the Letter "X"

x2 means two lanes , x4 four lanes ... like that

as you must have guessed it , x4 has more bandwidth than x2

example:
X2 has 1Gbytes/sec
X4 has 2Gbytes/sec

because of dependence on the lanes , the bandwidth is represented in terms of lanes (X)

I hope this solves your query

Ka beta ???

Hui hUi !!!

Added after 12 minutes:

Hi Bharat,
Loop back is just a fault finding state.basically used for debugging and testing.

In this state a master (tester) directs the DUT(connected via pci express) into loop back state
and then shoots all valid 10 bit symbols to the DUT ,the DUT should reply back with same 10bits, this way the initial level testing can be done, to validate the communication lines authenticity.

I wont complicate the matter by describing the details as to how the tester communicates to Dut to enter into LOOPBACK state and how it goes out from that state.

Hope you got some idea , it was a good question.


ok please ask more.

Regards
PCIE_fan

 

[bharat_in]

pcie configuration space diagram

Thanks nipoon..
it was nice explanation...

I am having some problem in understanding of BAR address configuration.
Can you please explain in detail with one example?

 

[s_prasan]

pci e ltssm

Hi Nipoon,

I m new to PCI express....so u r like my god.

so dear lord, can u tell some basics abt PCI express.........start from the beginning.

Thank you for ur blessings in advance

 

[ray123]

pcie loopback master

you should know PCI express flow control scheme.

 

[Thinkie]

pcie non-posted request

5GHz... wow...

 

[archillios]

pci nomenclature

hi nipoon,
I want to know some about PCI-e PHY, and PCI-e die-size cost, i/o number.

how do you think PCI-e integrated in base-band chips?

 

[carrot]

pcie loopback ltssm

Hi

What is Posted, Nonposted and Completion?

 

[eng_ahmed25]

lanes have analog transceivers

What is Posted, Nonposted and Completion ?

 

[bharat_in]

pci express flow control debugging

@eng_ahmed25
poested request are those in which the requestor don't wait for completion from receiver, whereas in non-posted request the requestor waits for the completion from receiver, which is the third type.

Each of them have different rules for processing.

 

[jsps]

pci express completion posted non-posted

which is better?PCI or USB in all aspects

 

[incisive]

what is pci express loopback

hello jsps,

comparing USB and PCI interms of usage is impractical, both serve differently for different purpose.

serial // parallel.

 

[jsps]

posted non-posted pci express

Dear Incisive,
I want to know in terms of speed, size, drivers needs and others.

regards
JSPS

 

[carrot]

pci express configuration space explained

Hi,

I need to know what is PIPE in PCIe.

am not looking for the expansion of PIPE. what i need is what is its main function in physical layer and how is useful? If any one is having a good document on this plz share it.

 

[sumit_techkgp]

pci express posted vs non-posted

This is too good of a wish. Can u tell why not use PCI.
Sumit

 

[modelsim62c]

why is it called a posted request pci

Hi,

I need to know what is PIPE in PCIe.

am not looking for the expansion of PIPE. what i need is what is its main function in physical layer and how is useful? If any one is having a good document on this plz share it.

Try a simple google-search!
Intel has a official specification document for PIPE (version 1.1) here:

https://www.intel.com/technology/pciexpress/devnet/resources.htm

Basically, the "PIPE" is an encapsulation of the SERDES-portion of the PCI-e PHY. It divides the PHY-functioinality into two separated domains: the low-level analog/transceiver portion (SERDES), and the link-layer side of the PHY state-machine (lane negotiation, training sequence, etc.) The PIPE-spec defines a standard-interface so any PIPE-transceiver (say, from Philips or TI) will connect to a PCI-e digital-core (example, from Synopsys Designware Foundation. )

It's kind of like what the GMII did for gigabit-ethernet (and AC97 did for PC soundcards) -- it lets the digital ASIC companies focus on doing everything "to the left" of the PIPE-boundary (i.e. host-side), and the high-speed analog transceiver companies do "everything to the right" of the PIPE-boundary (i.e. physical-link side.)