electronics_sky
Member level 3
RFIC design question
I am currently designing a LNA by using Si with 0.18um technology. My target is to design an LNA that has NF < 2db, Gain =15db and OIP3 >-3, I<4mA.
I am using a LC folded inductor source degeneration topology. Below are some of my questions:
1. Does folded technique will provide better noise performance than cascode technique?
2. I get a gain of -50dB for my design(i know it is wrong...), could i know what went wrong with my circuit?
3. Any idea how to improve NF of LNA?
4. Does adding a capacitor at Gate-Source terminal at first stage NMOS will help to reduce the NF (especially gate induced noise)?
Thank you in advance.
I am currently designing a LNA by using Si with 0.18um technology. My target is to design an LNA that has NF < 2db, Gain =15db and OIP3 >-3, I<4mA.
I am using a LC folded inductor source degeneration topology. Below are some of my questions:
1. Does folded technique will provide better noise performance than cascode technique?
2. I get a gain of -50dB for my design(i know it is wrong...), could i know what went wrong with my circuit?
3. Any idea how to improve NF of LNA?
4. Does adding a capacitor at Gate-Source terminal at first stage NMOS will help to reduce the NF (especially gate induced noise)?
Thank you in advance.