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Questions about qam and fir filtering

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Rfboy

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hi All,
I have a question about filtering a signal using fir filters.
I am tring to filter a qam signal with a root raised cosine pulsee shape filter and my filter have two inputs bit and 15 output bits. After the filter I have a DAC with a 10 bits resolution.

How have I to choose in the right manner the filter output bits to connect to the dac?

If the simbol rate is 10 MHz what have to be the frequency clock for the filter using a distribuited arithmetic parallel filter?

Is the right choice to have a filter with two input bits instead of two separate filters with 1 input bit?

Tx a lot.
 

zorro

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Hi RFboy,

You say that your input has 2 bits. Are there 2 bits for I and 2 bits for Q (i.e. using 16-QAM) or 1 bit for I and 1 bit for Q (i.e. 4-QAM=QPSK)?

In any way, the FIR filter coefficients should be scaled such that the peak output uses all the range of the register, and then connect the most significant bits to the DAC. If the DAC doesn’t have a 1/2 LSB offset, the result should be rounded in order to cancel the 1/2 LSB DC component (but this error is really small using 10 bits).

Regards

Z
 

Rfboy

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Hi Zorro, my system is a 16 qam so there are two bits for I and two bits for Q.
What is the right choice:

1)Implement two filters for I and two for Q one filters for each bit, and then summing the results to drive the DAC.

2)Implementing one filter with two input bits for I and one filter with two inputs bit for Q.

Tx for the suggestion about the scaling the coefficients.


Bye
 

zorro

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Hi Rfboy,

you should have two identical filters, one for I and one for Q. The values in the delay line are two bits wide (b1, b0) but they respresent numerical values that are , for instance:

b1 b0
11 => -3
10 => -1
00 => +1
01 => +3

If the coefficients are N bits, you would need in principle multipliers of N bits by 3 bits, because 3 bits are needed for represent the values from -3 to +3.
But it is possible to use a simpler logic instead of general multipliers. For instance, if the assignment between bits and values is as in the table above, the logic of multiplying the coefficient C by the datum (b1,b0) contained in a tap of the delay line would be:

R=C;
if b0==1 then R=R+2*C (i.e. add C shifted one place towards MSB)
if b1==1 then change the sign of R

Regards

Z
 

mwmmboy

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Hi Zorro,
thank you for your help !!!

Now I have another question:

The input signal of the filter has a data rate of about 8.592 MHz and I will use a 34.368 MHz sampling frequecy for the coefficient of the filter, what is the right frequency clock if I want to implement a fully parallel fir filter?

Do you know some issues of the Altera fir filter tool?

thanks
 

zorro

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Hi boy,

You use 4 samples per symbol. OK. An efficient way to implement the filter is in the form of an interpolator filter with an interpolation factor of 4 using polyphase filter structure. An interpolator filter accepts input data at some frequency and generates output at N times that data rate performing M/N operations instead of M, where M is the filter order.
See for example the chapter on Multirate Digital Signal Processing in the book of Proakis and Manolakis: Digital Signal Processing.
Sorry, I don’t know the @ltera fir filter tool.
Regards

Z
 

spweda

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Using polyphase filter is very complicated in the ASIC implementation. Just repeat input sample by 4 times and filter it. You need investigate the loss by this approximation.
 

zorro

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Hi spweda,

I don't agree with you. A polyphase filter is not more complicated than another FIR filter.
The repetition of the sample N times is equivalent to a polyphase interpolation filter with transfer function 1+z^-1+...+z^-(N-1); it is a lowpass filter. After that, you would need a filter that gives, cascaded with this one, the desired transfer function.
With a polyphase filter, the total order of the filter is approximately the same than the order of the abovementionned filter, but there is an important reduction (N times) in the number of required computations.
Regards

Z
 

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