katrin said:1, when I use poly layer to connect two transistor gates together(the distance is not long), is it OK? or I'd better connect the two gates together through metal layer?
katrin said:2, I want to draw the poly layer over the PDIFF or NDIFF layer, ( for example in an inverter, I draw a PDIFF around the NMOS, and then add some contacts on the PDIFF for guard ring, but I leave some PDIFF part without guard ring for wiring across it). I am not sure if it is a problem?
Because once I read that the poly layer across Diffusion layer are usually inteprated as gates, so in general people should avoid that?
RDRyan said:katrin said:2, I want to draw the poly layer over the PDIFF or NDIFF layer, ( for example in an inverter, I draw a PDIFF around the NMOS, and then add some contacts on the PDIFF for guard ring, but I leave some PDIFF part without guard ring for wiring across it). I am not sure if it is a problem?
Because once I read that the poly layer across Diffusion layer are usually inteprated as gates, so in general people should avoid that?
I don't think you should leave some PDIFF part without guard ring for wiring across it. You can add guardring around PDIFF and use high level layer metal for wiring across guarding.
katrin said:I have two questions regarding CMOS layout
1, when I use poly layer to connect two transistor gates together(the distance is not long), is it OK? or I'd better connect the two gates together through metal layer?
2, I want to draw the poly layer over the PDIFF or NDIFF layer, ( for example in an inverter, I draw a PDIFF around the NMOS, and then add some contacts on the PDIFF for guard ring, but I leave some PDIFF part without guard ring for wiring across it). I am not sure if it is a problem?
Because once I read that the poly layer across Diffusion layer are usually inteprated as gates, so in general people should avoid that?
secondlife said:2.Your question regarding gaurd ring is much serious when u r doing analog layout cause in that case you cant leave any part of PDIFF ungaurded but in case of inverters your version ll be OK.
katrin said:secondlife said:2.Your question regarding gaurd ring is much serious when u r doing analog layout cause in that case you cant leave any part of PDIFF ungaurded but in case of inverters your version ll be OK.
So in the analog layout, I should draw the guard ring all around the devices.
But usually I only add the guard ring for two sides for the device, and leave the other two sides unguarded for metal routing. Because it is easier to route the signal line also on metal one.
Are there any serious consequences, for example, some thing like large substrate noise?
Brittoo said:katrin said:secondlife said:2.Your question regarding gaurd ring is much serious when u r doing analog layout cause in that case you cant leave any part of PDIFF ungaurded but in case of inverters your version ll be OK.
So in the analog layout, I should draw the guard ring all around the devices.
But usually I only add the guard ring for two sides for the device, and leave the other two sides unguarded for metal routing. Because it is easier to route the signal line also on metal one.**broken link removed**
Research Projects, Institute of Microelectronics, University of Ulm
Are there any serious consequences, for example, some thing like large substrate noise?
hey katrin
Lke as i told u earlier, u need not add guardring on all the sides of a device blindlly. If it is a noisy device, then u need to protect ur circuit from this guy, so u need to enclose this device completely in a guradring. Again, for matched devices like the differential pair wherein matching is critical, complete guardring is preferred. U need to know which are the critical devices in your layout and add guard rings accordinlgly.
Every guard ring would have its effect upto certain distance like 15u or 30u , process dependent. So, you could get this info and add guardrings every 15u/ whatever distance accordingly for not-so-critical devices.
Regards
Brittoo
katrin said:I have two questions regarding CMOS layout
1, when I use poly layer to connect two transistor gates together(the distance is not long), is it OK? or I'd better connect the two gates together through metal layer?
2, I want to draw the poly layer over the PDIFF or NDIFF layer, ( for example in an inverter, I draw a PDIFF around the NMOS, and then add some contacts on the PDIFF for guard ring, but I leave some PDIFF part without guard ring for wiring across it). I am not sure if it is a problem?
Because once I read that the poly layer across Diffusion layer are usually inteprated as gates, so in general people should avoid that?
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