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#### airboss

##### Member level 3
Hi,

i've seen this block diagram for pipelined adc in many places but i'm really confused. please help me to understand this. we know this will be implemented by S/H capacitor circuit.

1)we see a 2X here. i guess this is because of capacitor charging transferring from sample phase to holding phase. is this correct?
2)many books mention that Vout = 2Vin-Vref. however, from the diagram i uploaded, it seems to me Vout=2*(Vin-Vref). what is my mistake? i know subtraction of output from DAC is done in holding phase. or should Vout=2*(2Vin-Vref)?

thank you!!

#### mince

##### Member level 5
If you look at the topology of the MDAC and do the analysis on the switch cap circuit, you can find that the output will be Vo = 2Vin - Vref for the 1.5 bit/stage architecture.

### airboss

Points: 2

#### satyasiva

##### Full Member level 1
this fig. does not correspond to 2vin-vref. it is for 1.5bit/stage.

### airboss

Points: 2

#### ronialeonheart

##### Junior Member level 1
The Vout = 2Vin-Vref mentioned by many books is not the Vin in this diagram. You can comprehend it as this, the first stage: Vout1=Vin±Vref, second: Vout2=2Vout1±Vref, ..., and Vout1, Vout2, ..., are not the Vout in your diagram. It's the voltage at the left side of the ×2 block.

Points: 2