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questions about pipeline ADC design

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airboss

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Hi,

We're working on a pipeline ADC design and we need some help here. Our question is on the spec of the op. We're asked to get settling correct within 1/4 LSB when we input a sine wave of frequency Fs/2 of full-scale amplitude.

1) we did ask our professor what that means but we didn't really get it. so can anybody help us understand what that means?
2) then the following question is regarding the design of op. we know there're some questions for GBW, error, gain, and so on so forth but our understanding is, those equations describe the linear settling or linear response. there's no specific equation taking care of the op spec and slew time. i wonder if we could do nothing by hand but just simulate it until we hit the settling requirement?

thank you!
 

lladnar23

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You can estimate the total settling time for slewing + linear settling by observing the following:
For an output voltage step Vstep, the opamp will slew for some fraction then linearly settle for the remainder. The derivative must be continuous between these two regions.
So for the slewing time, the derivative = SR = I/C. For the linear settling time, the derivative = Vlin/tau where Vlin is the portion of the voltage step that experiences linear settling (Vstep = Vslew+Vlin).
Then, the output voltage goes like this:
vo(t) = SR*t while t < t1
vo(t) = Vslew + Vlin(1-exp[-(t-t1)/tau] for t>t1
where t1 is the time when we change from slewing to linear settling. Equating the derivatives: (SR=I/C = Vlin/tau) lets us solve for Vlin (and thus Vslew, and t1).
 

    airboss

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satyasiva

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Generally wekeep 1/3 rd of the time for slewing and 2/3 rd for settling.
 

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