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Questions about NAND gate and latch in designs

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pravi

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1.why do we prefer NAND gate in our desing ..is it due to power and area or anyother factors.

2.if we replace latch enable signal by clock wat will be the difference

3, how latch takes less power and ff takes more power?
 

arunragavan

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Some Queries

A NAND gate has a lesser propagation delay when compared to the NOR gate, as in a NOR gate, the diffusion capacitance and gate capacitance, both are higher.
 

eeeraghu

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Re: Some Queries

1st- Bcos of power dissipation and less delay.
2nd. Clock is a type of enable signal to latch, if still considered depends on the input(the input is same as in previous case).
3rd. Power Dissipation depends on switching activity of clock, this might be the reason.
 

neoaspilet11

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Re: Some Queries

Hello

1.) NAND gates are primarily used in design because it is the building blocks of all logic gates. You can build OR, AND, NOT, XOR etc gates out of NAND. You can also build a basic SET - RESET latch on which all flip flops, static memory cells are based. Surely its derived functionality is immense. No wonder NAND has number 74XX00.

2.) If you replace the Latch Enable line (I assume this is a Latch or a D flip flop) with a clock, you cannot hold the current data! you just simply hold the data on and Off.

3.) Flipflops generally consumes more power than latches because they contain more gates than latches. This is because a flipflop has a decoder on its input to characterize the the flipflop. For example a D - Flipflop and and JK flip flop have the same set - reset cell but they have different decoders on its input.
 

tramp

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Re: Some Queries

hi neoaspilet11,
flipflop has a decoder ,please me what are this decoderWhat is there physical circuit consist of.
 

anjali

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Re: Some Queries

neoaspilet11 said:
Hello

1.) NAND gates are primarily used in design because it is the building blocks of all logic gates. You can build OR, AND, NOT, XOR etc gates out of NAND. You can also build a basic SET - RESET latch on which all flip flops, static memory cells are based. Surely its derived functionality is immense. No wonder NAND has number 74XX00.


using NOR also we can implement any logic.

2.) If you replace the Latch Enable line (I assume this is a Latch or a D flip flop) with a clock, you cannot hold the current data! you just simply hold the data on and Off.

for latch, if enable = 1, then output = input else no change in output.

if we replace the enable with a clk, why it can't hold data?

if we connect the enable with a clk, enable will be periodically asserted. is there anything wrong if clk is connected to enable?
 

neoaspilet11

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Re: Some Queries

Hello Anjali,

There is nothing wrong if you connect a clock to the ENABLE input of your latch. What I meant in my previous post is that the user has no control when to fetch the latched(or held data) because it is periodically opened and then closed. If a clock is connected to the ENABLE line of the latch, we are defeating the main function of the latch and that is to hold data and fetch it when we want to.
:D
Thanks
 

ee_joe

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Re: Some Queries

why the NOR has lower power and better propagation delay?

two input NAND and NOR both have four transistors,why is there any difference on their capacitances?

I think that NOR has a better tphl,but tplh is longer compared to NAND??

thanks & best regards
 

silencer3

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Re: Some Queries

NAND gates have equal RISE & FALL Times.

NOR gates have slow RISE time and fater falling time

From ASIC point of view, NAND takes advantage considering practical probelms at FAB level.
 

ee_joe

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Re: Some Queries

From ASIC point of view, NAND takes advantage considering practical probelms at FAB level.
hi silencer3,could u give me some details or example?NOR is uesd widely just because it's faster falling time?

thanks & best regards
 

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