pll mc 145151 fm
PDout is a tristate output, like a digital tristate gate. When there is no correction to be made, the output hovers at mid voltage.
For example, let say that you have a 5 volt power supply. When no correction is made, the PDout is held loosly at 2.5 volts.
If a phase correction needs to be made, the phase detector will connect the PDout pin either up to +5 volts, or down to 0V. It does this momentarily, once each clock cycle of the reference frequency at the phase detector. If the phase is way off, the momentary move up or down remains connected for a large % of the reference period. If the phase is almost there, the momentary move up or down remains connected for a small % of the reference period.
The PDout gate has current limiting in it, so the maximum current out is limited to +/-1 ma, +/- 0.1 ma, etc, depending on the chips design or how you hook it up/program it.
Somewhere in you loop filter there is a big capacitor that charges up or down depending on if + or - force is applied by the PDout.