Questions about logic mapping circuit graph

[promach]

For **broken link removed** , I have few questions on the following logic mapping circuit graph:

1. How are two gate circuits in Fig 1(a) being identical ?

2. For Fig 1(b), what does it exactly mean by The highlighted portion of the mapping graph can be explored during a depth-first traversal ?

3. For Fig 1(c), why there is an SR-latch ?

 

[std_match]

1. Every possible input combination will generate the same output for both circuits
2. I don't know
3. It isn't an SR-latch. The 'X'-marked symbols are "choice nodes", not logic gates.
(b) and (c) are "mapping graphs", not implementations.