Questions about how to use casex in Verilog

[billylee]

The following is an example of the casex statement
is this code ambiguous? Thank you!

always @(*) begin
casex (SumMsbSat1[16:13])
4'b0000 : SumMsbSat3 = SumMsbSat1[13:0];
4'b1111 : SumMsbSat3 = SumMsbSat1[13:0];
4'b0xxx : SumMsbSat3 = {1'b0, {13{1'b1}}};
4'b1xxx : SumMsbSat3 = {1'b1, {13{1'b0}}};
default : SumMsbSat3 = SumMsbSat1[13:0];
endcase
end

 

[lostinxlation]

Case statement is prioritized so that it looks fine to me, though you don't need default in this case.

 

[billylee]

thank you for your reply
also my coworker agree with you!

and Merry christmas~!