Questions about gated clk's

[mosgaard2000]

Hi,
I have tried to read about gated clocks in different posts, but haven't been able to find a good answer, so I create a new post.

I have a Clk_1 which I gate and call Clk_g. The block that runs on Clk_g read some signals from a block running on Clk_1.
My problem is I get some Hold-time violations because the outputs dissapears from the first block before the gated block can read it.

My output signals are only 1 clk wide - is that the problem and can it be solved or do I need to increase the width of the signal?

 

[haykp]

You certainly need to fix the hold violation otherwise you will lose the data. If you don't fix the hold violation then you will lose the data in your design, this will being to wrong functionality of your circuit. Also the hold violation can cause metastable states in your design, which is highly unwanted.

 

[ebuddy]

Once you put a gate on clock Clk_1 to generate Clk_g, Clk_g is later than Clk_1, which is why Clk_g has hold violation when it is capturing data launched by Clk_1. The solution is to balance the whole clock tree from Clk_1 root. Once you do that, the leaf cells on Clk_1 and Clk_g will have a minimized clock skew, and there should be no more hold time violation.

 

[mosgaard2000]

When you say I have to balance the whole clock tree from clk_1 root, what does you mean by that?
I have tried in Quartus to setup the Clk_g as a derived clk of Clk_1, but it doesn't seem to change anything. The strange thing is - if I say the derived clk has an offset of 0 ps compared to clk_1 all the warnings disappears, but in my simulations I still has timing problems.

Any advice?