#### gavin168

##### Junior Member level 3

**pll site:www.edaboard.com**

Hi, guys,

I am studying the Delta-Sigma Fractional-N PLL. there are somethings I don't understand.

First, what's the difference between the classical Fractional-N PLL and Delta-Sigma Fractional-N PLL? Is it like this case: For classical Fractional-N PLL, the swithing frequency of divisior ratio from N to N+1 is slow, while the switching frequency in Delta-Sigma modulator from N to N+1 is fast? And both the everage are same.

Second, what's the input and output of Delta-Sigma modulator? Normally, the divider is a counter in PLL, Is that the output of Delta-Sigma modulator is some bits which select the divisior ratio? ( For example, a counter with 3 bits input, when input is 100, divisior ratio is 5, if the counter input is 101, divisior ratio is 6. Is the delta-sigma modulator used to generator a output of 100 or 101 to switch the divisior from 5 to 6 ?)

There are many equations with little implemention schematic about the delta-sigma modulator in a lot of thesis. but they are too difficult to understand. Are there any documents talking about the delta-sigma modulator in transistor gate level.

thank you very much.