Questions about A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops

[promach]

For A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops ,

1. Why Notice that since FF''' is oppositely clocked and its data is sampled at the clock’s falling edge, its clock enabling signal X''' must be negated. ?
2. Why does the author state that : F''' is an ordinary FF where the internal XOR gate is connected between D''' and Q'''. ?

 

[promach]

I am building this clock gating cell using standard cells from FreePDK45. However, what is wrong with XOR2 (I44) ?

 

[BradtheRad]

XOR2 has its 'A' input wire lit up blue so it's hard to be sure the simulator recognizes if it has a proper connection to the wire between 2 red dots. Does the simulator turn joins red? That creates a question about the blue dots, whether it's a proper join.

 

[promach]

No, I already using the "save and check" feature inside virtuoso, it does not return any warning about connection issue. This is due to something else, I suspect.

--- Updated Nov 22, 2020 ---

Root cause found. See https://community.cadence.com/caden...1/freepdk45-usage-in-virtuoso/1371404#1371404

I might probably switch to using **broken link removed**