varunvats69
Junior Member level 1
Hey all,
I'm using a for loop in a sub-module of the SHA256 processor I'm designing. I haven't synthesized it yet but intend to do it very soon. Before going ahead I thought it worthwhile to get an idea of the hardware the synthesis tool will generate. I'm using Synopsys Design Compiler to synthesize my design.
My question: In the for loop in the file attached below, will DC generate 64 times the hardware required for a single for loop or will it loop through a single instance of the hardware 64 times, at every clock edge?
The structure I intend to generate is a shift register.
Note: I intend to change the statement:
reg [31:0]SHA256_const[63:0]; to wire [31:0]SHA256_const[63:0];
and the initial block to assign statements.
I'm using a for loop in a sub-module of the SHA256 processor I'm designing. I haven't synthesized it yet but intend to do it very soon. Before going ahead I thought it worthwhile to get an idea of the hardware the synthesis tool will generate. I'm using Synopsys Design Compiler to synthesize my design.
My question: In the for loop in the file attached below, will DC generate 64 times the hardware required for a single for loop or will it loop through a single instance of the hardware 64 times, at every clock edge?
The structure I intend to generate is a shift register.
Note: I intend to change the statement:
reg [31:0]SHA256_const[63:0]; to wire [31:0]SHA256_const[63:0];
and the initial block to assign statements.
