I was simply assuming that the solid state relays will never be turned on while a larger output voltage is present by working of the protection circuit. If this happens though with low impedance load, there can be a much higher energy dissipated due to the relative slow turn on and SOA exceedance is more likely.
If, you are using fets from Ali-express - you need to allow that failures will happen ...
I see no miller plateau, thus I assume this is "V_DS = 0 switching".So it is about 4mS to go from 5V to 6V. I just assume this is the window where the MOSFET goes from OFF-->SATURATION-->LINEAR(ohmic Rdson).
Hi,
I see no miller plateau, thus I assume this is "V_DS = 0 switching".
V_DS = 0 also means "now power".
If so, then please show a scope picture with V_DS = your max expectable signal voltage. (No need for very low load resistance, moderate load resistance is good). Then you will see true switching times.
Klaus
Should be described in every MOSFET application note... and is a well known phrase when talking about MOSFETs.What is a "miller plateau"?
Hi,
Should be described in every MOSFET application note... and is a well known phrase when talking about MOSFETs.
--> internet search, wikipedia, MOSFET application note....
In short: Flat horizontal line in V_GS chart when V_DS is moving, caused by C_DG --> miller capacitance.
Also important when looking for
* total gate charge... and thus important for
* swtiching times
Klaus
.............
I think I know what you are looking for. The waveform scope picture was taken with the drain D open, no load and no drive. With real voltage and real load, you expect when the Vds collapse or build up, there will be a kink on the Vgs wave form at the transition and you want to look at the kink. Am I right?
If that's what you are looking for, there's not much I can do about it, it's like that's the best I can do so far with the ASSR-V621. If you have a better circuit for the SS relay, let me know. Or else, this is the end of the road after changing the R4 from 5.1K to 2.5K. Only question remain is to find the MOSFET with the best SOA. Seems like the CSD19536 is the best I can find with 100V and Rdson < 2.8mohm.
Thanks
A useless consideration. Why should the source node float up or down without external current injected to it? And you completely forgot the MOSFET substrate diodes which clamp the source node to +/- (33 + 2*Ud) in your circuit. Finally, even without clamping diodes, the MOSFETs have a considerable avalanche energy absorbing capability, you need to drive larger currents to exceed it.
All-in-all it's quite unlikely that avalanche breakdown is the failure mechanism in your circuit.
The common source node is not floating, it's clamped by diodes.I worked with a lot of high voltage circuits, you'll be surprised any floating conductor can charge up.
The common source node is not floating, it's clamped by diodes.
The common source node is not floating, it's clamped by diodes.
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CSD19536 has higher avalanche energy and SOA rating with slightly lower gate charge. In so far I would prefer it.
But as long as you are still guessing about the actual failure cause, the relevance of these transistor parameters isn't clear.
Avalanche energy is specified in maximum ratings.
You are right about no diode clamping in negative direction, sorry for adding confusion. Anyway, I keep my point that there's absolutely no risk of uncontrolled charging.
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