The complete ckt is not shown, the SSR is in series with a power supply and load, the loop area of this total connection has inductance
showing the Vds at turn off may well shed light on the failure mechanism ...
As I already said in post#2 ... there is more inductance than just the PCB inductance.still have inductance, but is as low as I can make it based on limitation of the size and being 2 layers copper.
Hi,
0.5cm to 100cm is a factor of 200.
With a proportionality the inductance should go down from 1300nH to 6.5nH, but it goes down to 283only.
It's not even a factor of 5. And not even close to 200.
Nothing else I did say: While the resistance follows proportionality rule, the inductance does not.
As I already said in post#2 ... there is more inductance than just the PCB inductance.
Klaus
If you can show the G-S waveform, as in your earlier post, then surely you can show the D-S waveform at turn off - just make sure the scope ground and the amp power supplies do not have any other common connection.
If you can show the G-S waveform, as in your earlier post, then surely you can show the D-S waveform at turn off - just make sure the scope ground and the amp power supplies do not have any other common connection.
use differential measurement, using both channel 1 and channel 2 of the scope to hook onto the D and G respectively and use (Channel 1)-(Channel 2) to get the waveform.( On the scope is inverting one channel and add them together)
this should be pretty easy - trigger at 35V ... turn up the brightness / persistence to see fleeting effects ...
If we are to believe your earlier posts - you have already captured the G-S turn on - so it is difficult to see the issue here. As stated above set the rigger to +35V rising to capure the D-S turn off - turn up the brightness so you see everything - and then you can sketch it if you have to ...
The amplifier has no output current limiting, I presume it's able to destroy a switch transistor under circumstances, either by exceeding SOA characteristic or avalanche energy limit with load inductance.
If the 24 nF load is only an extreme test and not expectable in normal operation, I won't think about the problem that much. If you want safe behavior with any kind of load including short circuit, additional protection means are probably necessary.
If we are to believe your earlier posts - you have already captured the G-S turn on - so it is difficult to see the issue here. As stated above set the rigger to +35V rising to capure the D-S turn off - turn up the brightness so you see everything - and then you can sketch it if you have to ...
You wrote about missing clamping diodes in post #3 which brought up avalanche breakdown as possible scenario. If the diodes are in place and properly wired, I would exclude this failure mechanism.I have clamping diode D1.....D4 to ensure the voltage never goes 0.7V beyond +/-33V, so max Vds is less than 68V no matter what.
You wrote about missing clamping diodes in post #3 which brought up avalanche breakdown as possible scenario. If the diodes are in place and properly wired, I would exclude this failure mechanism.
Looking to the TK72E12N1 datasheet, I see a single pulse SOA limit of 30V/40A for 10 µs. According to the reported parameters, it might be exceeded when disconnecting the capacitive load.
Actual turn-off time can't be watched in your waveforms. It's surely short due to active discharge circuit but possibly not fast enough to keep SOA rating when disconnecting high currents.
Consider that the miller plateau in the Vgs waveform respectively the Vds risetime is indicating the interval of high power dissipation, it should be measured with load resistance and maximal output voltage.
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