What's the output stage power supply during the test? Does the amplifier implement instantaneous current limiting?
you say you use this circuit without fault for 4 years...and now a fet blows.......i reckon this is ESD problem...FETs are incredibly sensitive to ESD......i have worked in places that when PCBs with fets on them were reworked...even with esd mat and wrist strap being worn.....5% of the reworked boards would blow up....there is only one answer, and that is to handle fets as little as possible.
Some fets , from their manufacture , are more sensitive than others...the gate structure is microscopic, and impossible to make to great precision in every case...show a pic of your esd measures.
I have seen esd plugs going in to sockets where there was no earth in the socket!
OK - assuming there is not enough peak current to destroy the mosfets - that leaves 2, 3 things - 1:- over voltage at turn off with enough ckt current to melt the die at turn off,
or,
2:- not enough heatsinking - the current is overheating the mosfets and the weakest one fails first, or,
3:- some times there is too much current - again killing the weakest one first.
This is only true, when the Mosfet is fully switched ON.Even if you calculate 50A continuous current, that's only going to be 0.25W of power
show the Vds at turn off please ....
Hi,
several times you wrote about no (or low) inductance.
My opinion:
* "No inductance" does not exist.
* when there is inductance, then you have to expect higher voltage (higher than 32V)
* I don't expect "self oscillation" without inductance. So if you experienced self oscillation, then you experienced inductance. And if the inductance killed a Mosfet in the past ...
* large cross section does not reduce inductance (significantly)
* stranded wires do not reduce inductance (significantly)
***
You talk about switching speed. From the schematic and datasheet informations I expect way higher switching times. Especially at switching OFF. Did you do a true V_GS measurement to verify your values?
Higher switching times will reduce the voltage generated by an inductivity, but it may violate SOA specification. (Don't expect equal distribution of dissipated power over n Mosfets)
Klaus
Hi,
This is only true, when the Mosfet is fully switched ON.
But during rising and falling of V_GS the R_DS_ON generates a lot more heat.
Klaus
No. The resistance is low. Resistance depends on copper width, copper thickness and an length.The inductance of the plane should be very low.
Hi,
No. The resistance is low. Resistance depends on copper width, copper thickness and an length.
But impedance takes inductive impedance into account... and inductive impedance does not (much) care about copper thickness and copper width.
Regardless of copper width and copper thickness --> the inductance and thus the inductive impedance will be (alomst) the same.
But inductance cares about the return path of the current. And the returning current compensates the usual current und thus reduces the inductance.
In your case I assume a true GND plane willl be more effective to reduce the inductance than wide and thick copper areas.
Klaus
Ok, then the online calculators ... and me ... are wrong.No, inductance is proportional to the length/width in a very simple way
Hi,
Ok, then the online calculators ... and me ... are wrong.
https://chemandy.com/calculators/flat-wire-inductor-calculator.htm
(randomly chosen as first hit of an internet search. Never used it before)
Maybe you could post a formula or a link ..
Klaus
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