Question: VLSI Implementation of 256 to 8 encoder

[negreponte]

priority encoder 256-8

I need a block diagram of an implementation of 256 to 8 encoder?
(one-hot encoder)

Many thanks

 

[master.ro]

I think that a encoder is a combinational circuit not secvential.
Why you need a diagram for this?
Do you want to implement this in vhdl or what?

 

[negreponte]

Can anyone give me the 256-to-8 encoder block diagram?

many thanks

 

[ray123]

A 256-to-8 one-hot to binary encoder is just eight 128-input OR gates.
What kind of block diagram are you looking for?

 

[artem]

i think it both can be done in sequential and conbinational form . As sequential check this one (i did not simulate it) :

library ieee;
use  ieee.std_logic_1164.all;
use  ieee.std_logic_arith.all;

entity encoder is 				   
	port( din : in std_logic_vector(255 - 1 downto 0);
	dout: out std_logic_vector(7 downto 0));
end encoder;

architecture encoder of encoder is
begin
	process(din)			  
		variable temp: integer range 0 to 255;
	begin				  
		temp := 255;
		for i in 255 downto 0 loop
			if(din(i) = '1') then 
				dout <= conv_std_logic_vector(temp, 8);
				exit;			  
			end if;	 			  
			temp := temp + 1;
		end loop;	 
	end process;
end encoder;

Added after 1 minutes:

Note : to be able to avoid unwanted combinations of the code , the implementation does work as priority encoder - the first bit to find set - assign its value to out.

 

[negreponte]

A 256-to-8 one-hot to binary encoder is just eight 128-input OR gates.
What kind of block diagram are you looking for?

Can that implementation be more simple? any proposed implementations?

 

[artem]

implementation can not be simpler than information it does contain.
And how will be the truth table and circuit implementation of encoder done with
"encoder is just eight 128-input OR gates"?