question -> trimming method for relaxation oscillator

[cmos_ajay]

I have a question about Trimming of a relaxation oscillator based on charging and discharging of the capacitor. Attached is a schematic of it.

My desired oscillator frequency is 400kHz
To determine the change in frequency:
I vary the process (fast, slow, typical), temperature [-40 to 105 degree C], supply voltage V1 , Bias current I1, Vref by a certain percentage. The bias current I1 and voltage vref come from a bandgap reference. When I obtain the max. and min. value of frequency, I need to add or subtract currents flowing into the capacitor. This will bring the frequency back to the original value approximately.

a] Is this the correct trim procedure ?
b] How do I select the LSB size of frequency increment for this ?

Thanks .

 

[erikl]

a] Is this the correct trim procedure ?
b] How do I select the LSB size of frequency increment for this ?

a] Yes, I think so. Either current, or cap. Trimming the current needs less area, however.

b] Suppose your initial max. PVT frequency deviation could be ±30%, i.e ±120kHz,
and you need an (in-)accuracy of ≤1kHz, this would mean you need a 1/240 ≘ 8bit DAC current trim.
For a ±15% deviation and a ≤5kHz accuracy, a 5bit trim would be sufficient.