Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Question regarding SDF

Status
Not open for further replies.

cosmo_kramer

Newbie level 2
Joined
May 31, 2011
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,297
Hi all,
I have a question regarding SDF values.
Lets say for a design I dump an SDF without any constraints.
I also dump an SDF by defining a 500Mhz clock on one of the ports.
I also dump an SDF by defining a 20mhz clock on the same above port.

There are no other constraints other than the clock.
Now which SDF has the worst delay numbers of the three?
This is important as I use SDF for PT as well as ATPG sim's.
Now if we dump SDF based on mode and corner we cannot use it for SIM as ATPG has multiple modes in one pattern. Namely [SHIFT-TFT] - [CAPTURE] - [SHIFT OUT]. Now if we dump with mode and corner that which SDF to use for ATPG.

Also Generally how are SDF's dumped for using in functional/DFT SIM's?

Appreciate your inputs.
 

haykp

Member level 3
Joined
Oct 22, 2010
Messages
66
Helped
9
Reputation
18
Reaction score
9
Trophy points
1,288
Activity points
1,643
So you synthesize the design in mentioned 3 different cases ( with no constraint, with 500MhZ and with 20 MhZ) and dump the SDF.Please let me know if my understanding is correct.

My belief is that in no constraints case the SDF has the max delay.
 

cosmo_kramer

Newbie level 2
Joined
May 31, 2011
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,297
So you synthesize the design in mentioned 3 different cases ( with no constraint, with 500MhZ and with 20 MhZ) and dump the SDF.Please let me know if my understanding is correct.

My belief is that in no constraints case the SDF has the max delay.
Thanks for replying.
>>So you synthesize the design in mentioned 3 different cases
Actually synthesis is done with 500Mhz. but when I load the design in PT, I define constraints in three different styles.
1) Dump SDF without constraints
2) Dump SDF with 30Mhz
3) Dump SDF with 500Mhz

>>My belief is that in no constraints case the SDF has the max delay.
Can you explain why? This is not an incremental SDF(cross_talk analysis).
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top