module top (CLOCK, ENABLE, COUNT_OUT);
input CLOCK, ENABLE;
reg [3:0] COUNT=0;
output reg [3:0] COUNT_OUT;
always @ (posedge CLOCK) begin
COUNT <= ENABLE ? COUNT+1 : 0;
COUNT_OUT <= COUNT;
end
endmodule
NET "CLOCK" TNM_NET = "CLOCK";
TIMESPEC "TS_CLOCK" = PERIOD "CLOCK" 5 ns HIGH 50 %;
OFFSET = IN 2 ns BEFORE "CLOCK" ;
OFFSET = OUT 10 ns AFTER "CLOCK" ;
Slack: 0.846ns (requirement - (clock arrival + clock path + data path + uncertainty))
Source: COUNT_OUT_0 (FF)
Destination: COUNT_OUT<0> (PAD)
Source Clock: CLOCK_BUFGP rising at 0.000ns
Requirement: 10.000ns
Data Path Delay: 4.146ns (Levels of Logic = 1)
Clock Path Delay: 5.008ns (Levels of Logic = 2)
Clock Uncertainty: 0.000ns
Maximum Clock Path: CLOCK to COUNT_OUT_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
AD12.I Tiopi 0.944 CLOCK
CLOCK
CLOCK_BUFGP/IBUFG
BUFGCTRL_X0Y13.I0 net (fanout=1) 0.835 CLOCK_BUFGP/IBUFG
BUFGCTRL_X0Y13.O Tbgcko_O 0.900 CLOCK_BUFGP/BUFG
CLOCK_BUFGP/BUFG
OLOGIC_X1Y41.CLK net (fanout=6) 2.329 CLOCK_BUFGP
------------------------------------------------- ---------------------------
Total 5.008ns (1.844ns logic, 3.164ns route)
(36.8% logic, 63.2% route)
Maximum Data Path: COUNT_OUT_0 to COUNT_OUT<0>
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
OLOGIC_X1Y41.OQ Tockq 0.584 COUNT_OUT_0
COUNT_OUT_0
AB13.O net (fanout=1) 0.002 COUNT_OUT_0
AB13.PAD Tioop 3.560 COUNT_OUT<0>
COUNT_OUT_0_OBUF
COUNT_OUT<0>
------------------------------------------------- ---------------------------
Total 4.146ns (4.144ns logic, 0.002ns route)
(100.0% logic, 0.0% route)
module multi_cyc_test (
CLK,
RST_N,
ENA,
IN_DATA,
OUT_DATA
);
parameter IDLE = 2'b00;
parameter LOAD = 2'b01;
parameter COUNT = 2'b10;
parameter STORE = 2'b11;
input CLK;
input RST_N;
input ENA;
input [3:0] IN_DATA;
output [3:0] OUT_DATA;
reg [1:0] counter;
reg [3:0] reg_a;
reg [3:0] reg_b;
reg [1:0] current_state;
reg [1:0] next_state;
reg count_start;
reg reg_a_en;
reg reg_b_en;
wire count_done;
assign count_done = &counter;
assign OUT_DATA = reg_b;
always @(posedge CLK or negedge RST_N)
if (!RST_N)
counter <= 2'b00;
else if (count_start)
counter <= counter + 1;
always @(posedge CLK or negedge RST_N)
if (!RST_N)
reg_a <= 4'h0;
else if (reg_a_en)
reg_a <= IN_DATA;
always @(posedge CLK or negedge RST_N)
if (!RST_N)
reg_b <= 4'h0;
else if (reg_b_en)
reg_b <= ~reg_a; //from reg_a to reg_b, intermediate might have more combinational logic
always @(posedge CLK or negedge RST_N)
if (!RST_N)
current_state <= IDLE;
else
current_state <= next_state;
always @(current_state or ENA or count_done) begin
count_start = 1'b0;
reg_a_en = 1'b0;
reg_b_en = 1'b0;
case (current_state)
IDLE : begin
if (ENA) next_state = LOAD;
end
LOAD : begin
next_state = COUNT;
reg_a_en = 1'b1;
end
COUNT: begin
next_state = COUNT;
if (count_done) next_state = STORE;
count_start = 1'b1;
end
STORE: begin
next_state = IDLE;
reg_b_en = 1'b1;
end
default: begin
next_state = IDLE;
end
endcase
end
endmodule
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