Normally, every technology provided by the foundry (and definitely - 180nm from TSMC), comes with rules for current densities for electromigration.
These rules are described in electrical deign rule manual.
Also, it comes (at leas, for the advanced technology nodes) with special files describing these rules (ict, itf, etc.).
These current density rule are specified for metals / vias / contacts, but not for MOSFETs.
Once you find these rules, you have to apply them for your current flow simulation in power MOSFETs.
Simulating this is not a trivial task, because regular parasitic extraction + SPICE simulation does not work well, normally, for power FET layouts.