Question regarding I2C design

[ritzrulz07]

Hi all,

I have a query regarding I2C protocol for which I couldn't find an answer to in the specs.

-- Consider there are two masters and a single 10-bit slave operating on the I2C bus. Following a start condition (not a repeated start), one master drives a 10-bit write transfer whereas the other master drives a dummy 10-bit write transfer (Wdata-length = 0 , to be followed by a 10-bit read). In this case, both masters are trying to put the same address on the bus. The question is which of the two will win arbitration ?


Thanks in advance.

 

[FvM]

In the special case, arbitration has to be decided later. The other master must immediately free the bus whenever it detects a mismatch, see chapter I2C Spec chapter 8.2 Arbitration for details.

If the masters are each trying to address the same device, arbitration continues with comparison of the data-bits if they are master-transmitter, or acknowledge-bits if they are master-receiver.

In practice, it's rather unlikely that two masters start their I2C transaction simultaneously, but it's a border case, that has to checked to verify plausible operation of a multi-master enabled system.

 

[milind.a.kulkarni]

Hi FvM / ritzrulz07,

Can 10 bit read is possible trought I2C....Please let me know the procedure also....bcz i also want to read 10 bit of data from i2c

with regards,

Milind

 

[FvM]

I2C transactions are always in 8-Bit quantities. To read 10 bits, two consecutive 8-Bir read cycles have to be performed. The procedure is usually exactly documented in the device datasheet, also the required data alignment. Spare bits are often filled with status info or similar.

 

[ritzrulz07]

When I was mentioning a 10-bit read, I actually meant a read transfer addressed to a slave with 10-bit address.

Anyways, my query still remains unsolved. I was talking about the scenario when a master tries to put a dummy 10-bit addressed write (where there is no data transferred), followed by a repeated start condition. Simulatneously, the other master drives a normal 10-bit addressed write with data. The I2C spec mentions that there will be no arbitration between data & start-condition. So, does that mean that the master putting the data will win and the master trying to put a start-condtion will lose ?