It is a horrible mistake to come at a HDL with a software mindset, it just does not work that way.
In software you are telling a processor what to DO, in a synthesizeable HDL you are telling the chip what to BE, the difference is critical to understanding what is going on.
While I am an expert C programmer I find VHDL very much easier then Verilog simply because VHDL does not mentally make me think 'C'.
Start with thinking about the hardware architecture of what you want to accomplish and go from there, far more then in (relatively trivial) software, diagrams (including timing diagrams) and data flow drawings are where design starts.
Regards, Dan.