Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Question on WLM and DC topographical mode

Status
Not open for further replies.

vcnvcc

Full Member level 2
Full Member level 2
Joined
Jul 21, 2006
Messages
132
Helped
3
Reputation
6
Reaction score
2
Trophy points
1,298
Visit site
Activity points
2,210
I have a question on WLM -

Lets say in starting of project, which is brand new from scratch, and while running 1st pass DC, whether I'll be having WLM with me??
- if yes, who will provide it - is it library vendor? if no who is going to give?
lets say it WLM came from them, and in 1st pass I used it and used those DC's outputs in APR, now another question is do I have to generate WLM using in APR cycle? which again I'll be using in DC? is it correct/am i right?

- if no, then how do I have to start without WLM
lets say I have started without WLM, and used DC's output in APR, and in APR I have generated WLM, which in turn I'll be using it in DC..

Please share your inputs/info/knowledge, I'll highly appreciate, I did my homework searching on net. I would like to know that how it is used in Industry....
(at present I would like to know about WLM, I don't want to go for DC- TOPO) Thank you.
 

While running 1st pass DC, you have to specify the WLM model. These are usually available from the synthesis libraries. In the 2nd pass run using DC-TOPO, you should not specify these WLM models as that info is present in the DEF file. I don;'t understand what you mean by APR..
 

I assume you mean "auto place&route" by APR? (just use P&R - it is more conventional)

You apparently are wanting to avoid needing to use DC-Topo.
Do you actually have real WLM's available in the std-cell library you plan to use?
(most libs at 180nm and smaller no longer provide WLMs, and you thus are forced to use something like DC-Topo if you are concerned about avoiding iterations back and forth between P&R and DC to finally close timing for aggressive design goals)

However, if you are using a P&R tool such as ICC with physically-aware optimization, then you might not need to care because ICC will upsize or insert new buffers and so on to address loading and timing issues and so on.

The old-fashioned method is to use DC with WLMs for the initial pass, then do P&R, then export the netlist and *also* a script of "set_load" commands (for wire loads) and an SDF file (for wire delays) back to DC.
You then *incrementally* optimize in DC after reading in these "back-annotation" files, but you must also *disable* WLMs since you are no longer using them.
The flaw here is that if DC decides to insert a new buffer then the annotated information is no longer valid or not available for the new net, and you then risk another iteration again (and again and again and so on).
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top