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Question on Formal checking in Verification

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sudarsv

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Hi all

I am a graduate student specializing in VLSI design. I am trying to get acquainted with verification techniques and tools used in the industry. I am currently trying to understand the mathematical concepts of verification, like graphs, BDD, model checking, symbolic computation. But these concepts are more theoretical rather than practical. Can anyone let me know how are these concepts used in real world verification problems. Which tools are used for formal verification, what is the methodology that is followed in industry. Also please give me references to some sample projects on verification.

Thank you
 

Sample projects are really hard to find.

Check SMV tool

Also read the book applied formal verification by harry hoster.

Hope this helps.
 

Hai sudarsv

There are many tools for formal verification.. Let me give some hint

For STA Tools

Example :- Ets(encounter timing system from cadence), primetime etc..,

For DRC and LVS Verfication

Example :- Assura, calibre etc..,


This mainly deals with real time application..........


This may help u thanks:razz:
 

Hi Sudars,

For Verification the tools used are
1.Synopsys VCS tool
2.NCverilog tool (cadence)

The methodlogy for doing formal verification is by creating design under test(DUT) i.e, task based verification and the other methodlogy is by taking up some corner cases we can do formal verification

With Regards,
D.Raviteja.
 

Hi Raviteja,

I think i should add to that by saying that Synopsys VCS or Cadence Verilog are HDL simulators, they are not the only tools used in verification. So simulation is one aspect of verification. The other is equivalence checking and property checking of the design. For equivalence checking, the tools are
Cadence Conformal
Synopsys Formality

For Property checking, the tools are

Jasper's Jaspergold
Cadence Incisive
Synopsys Magellan
Mentor's Questa Formal

Note that these are all the tools. You don't have to know the tools first. First is getting the concepts.

I would recommend

https://www.amazon.com/Writing-Testbenches-Functional-Verification-Models/dp/0792377664
Amazon.com: Writing Testbenches using SystemVerilog (9780387292212): Janick Bergeron: Books
 

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