Question on delay insertion in DC synthesis

[tonyson]

Hi all,

When I run DC synthesis, I've set a set_max_delay constraint on a particular path. The synthesised gate level netlist seems only use INV1 in the delay chain. Therefore, a large number if INV1 is involved if the required delay is long. If I want to reduce the number of cells in a chain by using invertor or delay cell with longer delay. How can I achieve it except instantiation?

Thanks a lot

Tonyson

 

[bala_EE]

Why do you want to use some other cell? If so what do you think is possible to use other than INV?

 

[tonyson]

Because the synthesis shows that a chain of INV1 is needed to create a certain delay. But I found that in the library, there are several delay cell which can provide similar delay. So, I would like to know is there any way to create certain delay by using another cell (may be inverter, buffer or delay cell) which have longer delay such that less number of cell will be used.

Thanks

 

[yx.yang]

Because the synthesis shows that a chain of INV1 is needed to create a certain delay. But I found that in the library, there are several delay cell which can provide similar delay. So, I would like to know is there any way to create certain delay by using another cell (may be inverter, buffer or delay cell) which have longer delay such that less number of cell will be used.

Thanks

First: you may mean set_mix_delay. I think if set_max_delay, DC will not insert delay cells.
Second: There must be some delay cells in your library, you'd better use these cells. You can see that from the *.lib: the varivation of delay value of the delay cells in SS corner and FF corner is smaller than other cells with the same delay.

 

[ic_qiand]

Hi tonyson:

I think, maybe this CMD "set_dont_use" can be used to tell DC not to use certain STD Cells.