Question on Current Mirors

[Ravinder487]

Hi all,
I want to mirror 22.5 uA current from reference current mirror(Diode connected transistor shown in image attached).Reference current mirror is biased at gm/id =7.With gm/id=7 VGS should be equal to 450mV, as VGS=VDS for diode connected load,node 'p'(pin p in schematic) should also be at 450mV so as both the transistors(NM0 and NM1) are perfectly matched.
If NM1 is used as tail current souce VDS of 450mV should be allocated to it which results in zero output swing for my circuit.

 

[checkmate]

I have a question.

 

[dgnani]

Hi all,
I want to mirror 22.5 uA current from reference current mirror(Diode connected transistor shown in image attached).Reference current mirror is biased at gm/id =7.With gm/id=7 VGS should be equal to 450mV, as VGS=VDS for diode connected load,node 'p'(pin p in schematic) should also be at 450mV so as both the transistors(NM0 and NM1) are perfectly matched.
If NM1 is used as tail current souce VDS of 450mV should be allocated to it which results in zero output swing for my circuit.

You have to guarantee that the mirror NM1 is in saturation and yes strong inversion helps, you also have to take care that the Early voltage (either caused by channel length modulation or DIBL) will be high enough so that the the I-Vds curve is fairly flat in saturation. A flat curve in saturation means you can move around the drain voltage (which will be usually defined by the devices using the current provided by NM1) w/o changing the current the mirror provides.

 

[Ravinder487]

with r0 of 600Kohm for L=500n id-vds curve won't be absolutely flat and NM1 should be in saturation so as it acts like current source,but if there is shift in Vth of NM0 and NM1 due to PVT diode connected load will track its VGS and VDS so as to maintain same current and since VGS of both the transistors are equal there will be mismatch(in current) due to VDS,may be this will create problem!!

 

[dgnani]

600Kohm*22.5uA=13.5V !? what kind of supply are you planning to use?

Neglecting the above detail, increasing the length of the mirrors will reduce channel length modulation and make the Id-Vds curve flatter in saturation hence the current will depend less on the drain voltage, to reduce Vt mismatch one can interleave the mirrors layout.

A simple current mirror has limitations that can only be overcome by cascoding it, this will increase its output resistance at the expense of its output range.

 

[Ravinder487]

r0 is small signal resistance!!

 

[leo_o2]

You supposed the current will perfectly match. However, it will not be true. Actually, NM1's drain voltage will change according to its load to have a current balance and leave the current deviated from the current of NM0.

with r0 of 600Kohm for L=500n id-vds curve won't be absolutely flat and NM1 should be in saturation so as it acts like current source,but if there is shift in Vth of NM0 and NM1 due to PVT diode connected load will track its VGS and VDS so as to maintain same current and since VGS of both the transistors are equal there will be mismatch(in current) due to VDS,may be this will create problem!!

 

[dgnani]

r0 is small signal resistance!!

that makes more sense. Still the same remarks apply increase the length of the mirrors to increase your r0 <=> flatten the Id-Vds curve in saturation

Current matching will improve with device area as well

 

[Ravinder487]

In razavi,s Analog IC design book more stress is laid on VDS matching of mirroring transistors,I don't understand why!!
Any how due PVT VDS of diode connected load will be different from mirroring transistors then why do we need to bother much about matching in VDS?

 

[dgnani]

If your current matching requirements are very stringent then increasing L will become useless at some point, one can then try to add passive or active elements to keep the drain voltages of the mirroring FETs in a narrow range. This will limit the mismatch due to finite output resistance. This is a systematic mismatch. Other sources of systematic mismatch will be PVT. The drain voltage control has to behave well under those global variations.
In addition you will get sources of random mismatch (e.g. Vt mismatch) which you can deal with by increasing size, proximity, interleaved layout, etc