Question on asserting an asynchronous reset

[sree205]

Hi all,
I've a basic question on asynchronous reset. as soon as reset is sampled, entire system goes to initial state within a clock pulse. so, is there any necessity for reset to stay asserted for multiple clock pulses ? i'm not able to think of any scenario where that might be required. can anybody think of such a scenario ?

 

[semiconductorman]

Re: question on reset

Well there may be a few array of registers which need to be serially written to '0' , but in most cases it it the clock controllers and plls which dictate how long the reset should be high also if there are multiple clock domains you may need to take a few things into consideration .

 

[quan228228]

Re: question on reset

the 8051 needs multi clock cycle to reset state.

 

[mssajwan]

question on reset

most of the time it takes certain number of clocks for the whole system to get initialized.