Question on a CMOS Inverter!

[vlsi_whiz]

We all know that the CMOS inverter consists of a PMOS transistor on top connected to Vdd and NMOS at the bottom connected to Vss or GND.

What if the NMOS was connected to Vdd and PMOS to Vss or GND? Would this configuration work as a Buffer or will it not work at all?

What do you think...am not sure as to how this circuit will behave..Suggestions, comments most welcome.

 

[Alles Gute]

In my opinion, it may work to some extent, but the output will be in the range (Vin+VthP)<Vout<(Vin-VthN) because NMOS and PMOS both need some overdrive voltage.

 

[tarkyss]

because the input is between gnd and vdd, if the nmos connected to vdd, when the nmos will be on?
the same is for pmos,
so i dont think it can work

 

[vlsi_whiz]

Considering the structure of a MOS transistor, it is symmeteric, ie, the Drain and Source terminals can be interchanged. For a PMOS transistor, the source is at a higher potential than the drain and, for NMOS the drain is at a higher potential than the source ( the source is always at the lowest porential in the circuit).

Keeping this in mind and now looking at the configuration I had mentioned earlier, the drain and source of the PMOS and NMOS can be interchanged. So, now the transistors should be baised properly at some point and therefore should work as a kind of buffer.

Correct me if I'm wrong!

 

[rakeshnunna]

I guess the configuration will work as a weak buffer.The rail to rail swings cant be achieved using the configuration

 

[carrot]

Hi

If NMOS was connected to VDD & PMOS to GND, the whatever the input u give, the output will have the same i.e.. the output will remain the same as input, but with a difference in leakage.

 

[visualart]

I think the connect is used as the diode for the protect.

 

[dBUGGER]

Hi,
This combination indeed works as a buffer. But the disadvantage is that the swing is not 0 to 5v. You will not achieve full 5v o/p if you give 5 v i/p. It will be less that the 5v by threshold level of the transistor.
Similarly the logic low level will not be a perfect '0' v it will be more than 0 by the threshold voltage.
So now your noise margins may reduce and also power consumption of the circuit will be more.
Use two inverters if you want to make a buffer.

best regards,

 

[Ikon]

Hi,

If we connect the NMOS transistor to VDD and PMOS transistor to VDD ( opposite to that of a Inverter) , it acts as a Weak - Non- Inverting Buffer.

The o/p swing will not be from VDD to VSS inspite of that it will be Only
(VDD-VthNMOS ) to (VSS-vthPMOS). So u will not be able to get the desired o/p swing and thus U should aviod connecting i such a manner.

The O/p swing is b/n (VDD-vthNMOS) and (VSS-vthPMOS) because
NMOS IS A POOR PASSER OF LOGIC 1 AND PMOS IS A POOR PASSER OF LOGIC0.

Hope this helps

With Best Regards

Added after 4 minutes:

I mean to say

PMOS ---> Bad passer of 0 and good passer of 1
NMOS----> Bad passer of 1 and good passer of 0

 

[funster]

your circuit can work, but output voltage is not ideal,

high output level will be VDD - Vtn, low output voltage is

VSS + Vtp, so we use two inverter to construct buffer to

output nearly ideal output voltage.


best regards

We all know that the CMOS inverter consists of a PMOS transistor on top connected to Vdd and NMOS at the bottom connected to Vss or GND.

What if the NMOS was connected to Vdd and PMOS to Vss or GND? Would this configuration work as a Buffer or will it not work at all?

What do you think...am not sure as to how this circuit will behave..Suggestions, comments most welcome.

 

[beckchm]

when you have the best configuration ,why choosing the worse one ?

 

[e2e]

what company do you work for -- i want to be sure not to recommend any chip you may work....seriously who do you work for and what kind of products are you making?

 

[rmy]

the inverter will be working as a buffer but it does not have the full output swing in the output voltage between VDD and VSS.

 

[vlsi_whiz]

Well, Thanks for your replies. Most of you are right. The circuit works as a buffer, a weak buffer. Its operation is confirmed with Tanner and also using layout. As mentioned, the output swings are very less.

As for E2E and beckchm, am not designing such buffers for commercial use or anythin.. I know how to design buffers and other ckts really well. Just that this is a very famous interview question asked in VLSI interviews here.. and wanted to find out how many of you would think straight and analyse the ckt.

What would you say if you were asked this Q in an interview? Would you laugh at the interviewer and tell him he's a screwed up designer and that all his ckts will never work?? Never underestimate others..just because they ask what you might call a stupid Q!!! These kind of stupid Q's are often asked in interviews to check out how you would think and also to find out your power of analysis.

Cheers!

 

[jackson_peng]

this circiut work as an output stage in analog circuit, for it has the benifit of keeping the signal phase.

but it is no use in the digital work, because it can't achive the rail-to-rail property, which mean it cant turn-off the downstream gate for power control.