kimjin
Member level 3
i simulation the verilog code in modelsim,using the altera flex10k10 fpga,error occured during the simulation ,a internal signal goto 'Z' in sometime,and the logic become wrong,i don't know whether it's the simulator' error or my code have question,if at the clock's posedge,the sig's sample value is 'Z',will the error occur?
who have met the error,please help me?thank you.
who have met the error,please help me?thank you.