question in vhdl code

[hossam abdo]

Dear colleges

this is simple code

"entity ex is
port (addrs : in STD_LOGIC_VECTOR(7 downto 0);
data : in STD_LOGIC_VECTOR(31 downto 0);
MBSS0,MBSS1,MBSS2,MBSS3 : out STD_LOGIC);
end ex;

architecture Behavioral of ex is
signal block0,block1,block2,block3 : integer;
begin
block0 <= conv_integer(STD_LOGIC_VECTOR(addrs(4 downto 0)));
block1 <= block0 + 1;
block2 <= block0 + 2;
block3 <= block0 + 3;

MBSS0 <= data(block0);
MBSS1 <= data(block1);
MBSS2 <= data(block2);
MBSS3 <= data(block3);
end Behavioral;"

when write the code as previous this error occured in model sim
Fatal error in Architecture behavioral at ex.vhd line 51

but when putting block0,block1,block2,block3 as variables in process.. no error occurred

i think that is wrong to putting them as signal , they must be variable?


also the used slices is 5 %
4 input LUT 5%
Number of bonded IOBs 33 %
is this large or no?

thanks.

 

[skal81]

If I remember correctly, you cannot use "signal" type to address a bit of a vector. That's probably the origin of the error.
This restriction is related to the synthesis, but the syntax error is detected at simulation level (which is not always the case, so one need to be careful).