Question:High speed dsp (about 350MHz) on virtex5

[soheyl]

Hello
I want to implement a high speed(about 350MHz) dsp (iir filters, fir filters and ect.) system on virtex5; My system clock is about 80MHz. Input data rate is 350MHz(10 to 14 bits). How can i do this?
thanks

 

[ring0]

You need to multiply your system frequency using CMT (Clock Management Tile), so that your FPGA would operate on frequency equal or higher than 350 MHz.

 

[soheyl]

yes. I can do this with dcm. But main questation is: Can this fpga operate in this frequency? There will be some problem in routing.
How can I do this with system generator?

 

[lucbra]

V5 is can operate at up to 500MHz internally. Also the DSP blocks can run at the same speeds.
But yes, you will need to put some constraints to your high speed part of the design.

Regards

Added after 1 minutes:

And you will need to hand craft quite a bit of the design.

 

[ring0]

Another approach that can be used is polyphase filtering, to emulate 350 Megasamples per second on low system frequency.

 

[soheyl]

Another approach that can be used is polyphase filtering, to emulate 350 Megasamples per second on low system frequency.

can you give me more information about "polyphase filtering" and its implementation on fpga?
Thanks

Added after 1 hours 25 minutes:

Another approach that can be used is polyphase filtering, to emulate 350 Megasamples per second on low system frequency.

Can i implement iir filter with polyphase filtering?

 

[seafrn]

It's a good idea to do polyphase filtering to lower clock speed but at the expense of more area. You can go to wikipedia to check what is polyphase. but be prepared it is kind of complicated.

There are other well-known ways to fit high speed processing in FPGA. You can google searching it. My two cents is in **broken link removed**