question for ADDER complexity

[layowblue]

Hi All

I need to add a 21-bit signal to a 32-bit signal, and it won't generate carry bit[33].
Since the clock is really fast, I'm trying to figure out how complex the ADDER logic might be, based on standard library from TSMC. For example, will the critical path have more than 21 NAND-like level of combo cells?

Can some body shed lights on how to calculate or estimate it?

Thanks

 

[ThisIsNotSam]

adder complexity doesn't depend solely on the library. it depends on the template that the synthesis tool will adopt. You can make a synthesis script really fast and find out what choice you have.