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[question] DRC fix in SOC Encounter

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gerade

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Hi, All,

it seems that SOC encounter doesn't have quite good capability to fix DRC, or?

In my run, a module around 2x2 has almost 800 DRC error, and most of them are apparently not difficult to get fixed.
I really go through every page of the User manual and Cadence website, and do not find anything regarding DRC fix in SOC Encounter. But I still don't believe Encounter will be so lousy in this aspect.

Can you give me some hint on this point?

Thanks a lot!
:?:
 

aravind

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u must export the def file from encounter
and fix all DRC error in assura or calibre(mentor)
encounter wont fix DRC violation.
 

gerade

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thanks,

yes, this is what I am doing know, I load the gds into icfb and fixed them interactively with calibre drc rve. Luckily there are not some many DRC errors.

RGDs
 

leeenghan

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Hi,

Encounter is weak on DRC related to the metal overhang for the power router.

Beside that, if both the LEF technology and LEF files are good, then I ould said not DRC should be expected. If you can show us the type of DRC errors that Encounter make, perhaps we can know what need to be fixed.

Regards,
Eng Han
ww.eda-utilities.com
 

yonehara

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Hi, i have found many DRC problems after nano route. Such as open and antenna violations. Open Violation is the most frequent and I dont know what I have to do to solve this problem!! My doubt is, from when I can extract the GDSII and further files to solve this on Virtuoso? Can i solve this on virtuoso? What is the solution for my problem?
 

rca

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If your technology LEF file is provided with your std cell you should have no DRC visible by Encounter.
I never provide a gds with more than 10DRC errors for 100kgates design 75% std celle density, antenna could be more difficult when no place is available for routing and diode placement.
 

yonehara

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Well, LEF file is provided, you are talking about IMPORT DESIGN STAGE, right? if yes, anyway i got these DRC vios. What is the explanation about it? my design is simple, no hard macros, only the std cell block to floorplan i'm a noob (first big project) and design density is something about 75% or less. Another problem i've faced out is the congestion red diamonds after trial route, i can increase die area infinitely, they will reduce congestion diamonds but I will find some ones always!

Thank you!
 

rca

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Did you used no special option during the placement ?
 

yonehara

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neither pre nor in-place optimization.. this is the problem? What happen in in-place and pre-place optimization?
I will try this way, with both optimization.
 

rca

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you define high effort for congestion issue during pre-post placement

---------- Post added at 10:26 ---------- Previous post was at 10:25 ----------

if you already seen congestion violation after placement, there is an issue to solve before going forward.
you could also used padding feature on module/cell/instance..
 

soloktanjung

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Hi Rca,

Can you please explain me "congestion violation" after placement. I have many process antenna violations and dont know what to do then after trying many things in the soce guide.

Thank you for you time.

Hairo
 

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