Question about Xlinx Timing Constrain

[EDA_hg81]

Few modules in my code such as module 1, module 2 and module3.

Only module 1 and module 2 have physical connections.

But why Xlinx Timing Constrain analyzer shows all timing errors even for connections between module1 and module 3?

They should not be connected.

Why?

All your suggestions are appreciate.

 

[EDALIST]

you probebly use a common clock signal for all of them.

 

[Blowfishie]

EDALIST's answer sounds right, but if you want to understand timing constraints and errors, I have just the thing for you...

Here is a link to a SUPERB document describing static timing in Xilinx devices, how to set up constraints and what they do. It also covers the error messages and the timing reports so that you can optimise your logic.
**broken link removed**

 

[jay_ec_engg]

If not clock then atleast there will be one common signal connected to both the blocks....and the STA tool will show that path... you may see that in the unconstraint path report...

 

[EDA_hg81]

Do you know hot to change Logic level in xilinx ISE?

 

[shoufeng_luo]

You can double click the submenu "assign package pins" and you can select the logic type.